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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|30% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|30% Load
Date / Time 12/10/2015 6:14 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\30% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.7802%
eta_min 95.7802%
Frequency(CLK) 79.8614k
gain_crossover_freq 4.85813k
gain_margin 26.3027
gmargin_min 26.3027
gxover_min 4.85813k
ILOAD
AVG
1.50648
MIN
1.50553
MAX
1.50734
RMS
1.50648
PK2PK
1.80466m
iload_min 1.50648
ISRC
AVG
105.307m
MIN
-579.544m
MAX
630.114m
RMS
321.884m
PK2PK
1.20966
min_phase 44.6237
min_phase_freq 4.85813k
phase_crossover_freq 31.7591k
phase_margin 44.3653
pmargin_min 44.3653
Power(LOAD) 36.301
Power(SRC) 37.9003
sw_freq_min 79.8614k
VLOAD
AVG
24.0966
MIN
24.0816
MAX
24.1101
RMS
24.0966
PK2PK
28.5447m
VSRC
AVG
359.989
MIN
359.937
MAX
360.058
RMS
359.989
PK2PK
120.966m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1101) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0816) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (26.3027) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (44.3653) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac34_2034.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop34_2000.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop34_1990.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop34_1981.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop34_1995.sxgph
Other SXGPH Files
default#2023#pop simplis_pop34_2023.sxgph
Modulator#pop simplis_pop34_2028.sxgph