* SCHEMATIC : ..\..\LTC3406B - DVM ADVANCED.sxsch
* TESTPLAN : dvm_advanced.testplan
* ORIGINALTP: 6.0_a_sampling_of_the_syncbuck_1in_1out.testplan
* DATE : 2015-12-10
* TIME : 5:39 PM
* REPORT DIR: D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM
* NUM TESTS : 17
* HTMLTITLE : SIMPLIS DVM Test Report Overview
*
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|Light Load
* PROGRESS : 1 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|50% Load
* PROGRESS : 2 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Nominal\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|100% Load
* PROGRESS : 3 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Nominal\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Minimum|Light Load
* PROGRESS : 4 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Minimum\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Minimum\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Minimum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Minimum\Light Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Minimum|50% Load
* PROGRESS : 5 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Minimum\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Minimum\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 9 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Minimum|100% Load
* PROGRESS : 6 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Minimum\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Minimum\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Minimum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : WARN
* REPORT : Ac Analysis\Bode Plot\Vin Minimum\100% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Maximum|Light Load
* PROGRESS : 7 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Maximum\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Maximum\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Maximum\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Maximum\Light Load\report.txt.html
* TEST TIME : 9 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Maximum|50% Load
* PROGRESS : 8 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Maximum\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Maximum\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Maximum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Maximum\50% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Maximum|100% Load
* PROGRESS : 9 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Bode Plot\Vin Maximum\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Maximum\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Conducted Susceptibility|Vin Nominal|Light Load
* PROGRESS : 10 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Conducted Susceptibility\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 9 seconds
*
* TEST : Ac Analysis|Input Impedance|Vin Minimum|50% Load
* PROGRESS : 11 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Input Impedance\Vin Minimum\50% Load/report.txt
* DECK : Ac Analysis\Input Impedance\Vin Minimum\50% Load\input.deck
* INIT : Ac Analysis\Input Impedance\Vin Minimum\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Input Impedance\Vin Minimum\50% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Output Impedance|Vin Maximum|100% Load
* PROGRESS : 12 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Ac Analysis\Output Impedance\Vin Maximum\100% Load/report.txt
* DECK : Ac Analysis\Output Impedance\Vin Maximum\100% Load\input.deck
* INIT : Ac Analysis\Output Impedance\Vin Maximum\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Output Impedance\Vin Maximum\100% Load\report.txt.html
* TEST TIME : 9 seconds
*
* TEST : Transient|Step Load|Vin Nominal|50% Load to 100% Load
* PROGRESS : 13 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Transient\Step Load\Vin Nominal\50% Load to 100% Load/report.txt
* DECK : Transient\Step Load\Vin Nominal\50% Load to 100% Load\input.deck
* INIT : Transient\Step Load\Vin Nominal\50% Load to 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Step Load\Vin Nominal\50% Load to 100% Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Transient|Step Line|Light Load|Vin Minimum to Vin Maximum
* PROGRESS : 14 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Transient\Step Line\Light Load\Vin Minimum to Vin Maximum/report.txt
* DECK : Transient\Step Line\Light Load\Vin Minimum to Vin Maximum\input.deck
* INIT : Transient\Step Line\Light Load\Vin Minimum to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Transient\Step Line\Light Load\Vin Minimum to Vin Maximum\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Transient|Startup|50% Load|0V to Vin Maximum
* PROGRESS : 15 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Transient\Startup\50% Load\0V to Vin Maximum/report.txt
* DECK : Transient\Startup\50% Load\0V to Vin Maximum\input.deck
* INIT : Transient\Startup\50% Load\0V to Vin Maximum\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Transient\Startup\50% Load\0V to Vin Maximum\report.txt.html
* TEST TIME : 7 seconds
*
* TEST : Transient|Short Circuit|Vin Minimum|Light Load to Short Circuit
* PROGRESS : 16 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit/report.txt
* DECK : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit\input.deck
* INIT : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit\input.deck.init
* STATUS : RUN
* RSTATUS : RUN
* REPORT : Transient\Short Circuit\Vin Minimum\Light Load to Short Circuit\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|50% Load
* PROGRESS : 17 of 17
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_39_PM\Steady-State\Steady-State\Vin Nominal\50% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\50% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 8 seconds
*
*
* TOTAL TIME: 171 seconds
* TESTS RUN : 17 of 17