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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|25% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|25% Load
Date / Time 12/10/2015 6:07 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\25% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.8735%
eta_nom 95.8735%
Frequency(CLK) 87.7041k
gain_crossover_freq 4.62713k
gain_margin 27.3682
gmargin_nom 27.3682
gxover_nom 4.62713k
ILOAD
AVG
1.25552
MIN
1.25487
MAX
1.25608
RMS
1.25552
PK2PK
1.20948m
iload_nom 1.25552
ISRC
AVG
83.0656m
MIN
-539.808m
MAX
585.954m
RMS
291.509m
PK2PK
1.12576
min_phase 53.838
min_phase_freq 4.62713k
phase_crossover_freq 33.6327k
phase_margin 53.811
pmargin_nom 53.811
Power(LOAD) 30.2543
Power(SRC) 31.5564
sw_freq_nom 87.7041k
VLOAD
AVG
24.0969
MIN
24.0845
MAX
24.1074
RMS
24.0969
PK2PK
22.9021m
VSRC
AVG
379.992
MIN
379.941
MAX
380.054
RMS
379.992
PK2PK
112.576m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1074) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0845) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (27.3682) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (53.811) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac5_294.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop5_260.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop5_250.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop5_241.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop5_255.sxgph
Other SXGPH Files
default#283#pop simplis_pop5_283.sxgph
Modulator#pop simplis_pop5_288.sxgph