back to overview ▲

» DVM Test Report: Steady-State|Steady-State|Vin Minimum|70%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|70%
Date / Time 12/10/2015 5:47 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinMinimum\70%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 73.6386%
Efficiency_Min 73.6386%
Frequency(CLK) 955.643k
ILOAD
AVG
1.0504
MIN
1.0479
MAX
1.05274
RMS
1.0504
PK2PK
4.83945m
ISRC
AVG
477.352m
MIN
381.224u
MAX
1.31674
RMS
717.402m
PK2PK
1.31636
Power(LOAD) 1.58144
Power(SRC) 2.14757
VLOAD
AVG
1.50556
MIN
1.50198
MAX
1.50892
RMS
1.50556
PK2PK
6.9365m
VSRC
AVG
4.49952
MIN
4.49868
MAX
4.5
RMS
4.49952
PK2PK
1.31636m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50892) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50198) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop30_1034.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop30_1024.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop30_1029.sxgph
Other SXGPH Files
clock#pop simplis_pop30_1016.sxgph