* SCHEMATIC : ..\..\4.2_LTC3406B - DVM ADVANCED.sxsch
* TESTPLAN : dvm_advanced.testplan
* ORIGINALTP: line_and_load_regulation.testplan
* DATE : 2015-12-10
* TIME : 5:48 PM
* REPORT DIR: D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM
* NUM TESTS : 7
* HTMLTITLE : SIMPLIS DVM Test Report Overview
*
*
* TEST : Steady-State|Input 1 Minimum Voltage, Output 1 100% Load
* PROGRESS : 1 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Steady-State\Input 1 Minimum Voltage, Output 1 100% Load/report.txt
* DECK : Steady-State\Input 1 Minimum Voltage, Output 1 100% Load\input.deck
* INIT : Steady-State\Input 1 Minimum Voltage, Output 1 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Minimum Voltage, Output 1 100% Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Input 1 Maximum Voltage, Output 1 Light Load
* PROGRESS : 2 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Steady-State\Input 1 Maximum Voltage, Output 1 Light Load/report.txt
* DECK : Steady-State\Input 1 Maximum Voltage, Output 1 Light Load\input.deck
* INIT : Steady-State\Input 1 Maximum Voltage, Output 1 Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Maximum Voltage, Output 1 Light Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Input 1 Nominal Voltage, Output 1 100% Load
* PROGRESS : 3 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Steady-State\Input 1 Nominal Voltage, Output 1 100% Load/report.txt
* DECK : Steady-State\Input 1 Nominal Voltage, Output 1 100% Load\input.deck
* INIT : Steady-State\Input 1 Nominal Voltage, Output 1 100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Nominal Voltage, Output 1 100% Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Input 1 Nominal Voltage, Output 1 Light Load
* PROGRESS : 4 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Steady-State\Input 1 Nominal Voltage, Output 1 Light Load/report.txt
* DECK : Steady-State\Input 1 Nominal Voltage, Output 1 Light Load\input.deck
* INIT : Steady-State\Input 1 Nominal Voltage, Output 1 Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Nominal Voltage, Output 1 Light Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Input 1 Minimum Voltage, Output 1 50% Load
* PROGRESS : 5 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Steady-State\Input 1 Minimum Voltage, Output 1 50% Load/report.txt
* DECK : Steady-State\Input 1 Minimum Voltage, Output 1 50% Load\input.deck
* INIT : Steady-State\Input 1 Minimum Voltage, Output 1 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Minimum Voltage, Output 1 50% Load\report.txt.html
* TEST TIME : 7 seconds
*
* TEST : Steady-State|Input 1 Maximum Voltage, Output 1 50% Load
* PROGRESS : 6 of 7
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Steady-State\Input 1 Maximum Voltage, Output 1 50% Load/report.txt
* DECK : Steady-State\Input 1 Maximum Voltage, Output 1 50% Load\input.deck
* INIT : Steady-State\Input 1 Maximum Voltage, Output 1 50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Input 1 Maximum Voltage, Output 1 50% Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Final Math
* PROGRESS : 7 of 7
* SIMULATOR : simplis
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Final Math/report.txt
* SIMULATOR : N/A
* STATUS : SKIP
* RESULT : Line and Load Regulation (Input 1, Output 1)=3.7136213%
* RESULT : Load Regulation (Output 1) for Output 1=0.0079734219%
* RESULT : Line Regulation (Input 1) for Output 1=0.0059800664%
* EXECUTED : simplis_dvm_advanced_testplan_line_and_load_regulation_post_process, returned 0 scalars, 0 specs, 0 statistical scalars, 0 statistical specs
* RSTATUS : SKIP
* REPORT : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_48_PM\Final Math/report.txt
* TEST TIME : 0 seconds
*
*
* TOTAL TIME: 51 seconds
* TESTS RUN : 7 of 7