Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|100% Load |
Date / Time | 12/10/2015 6:13 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\100% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.2409% |
eta_max | 95.2409% |
Frequency(CLK) | 92.7188k |
gain_crossover_freq | 5.88124k |
gain_margin | 18.429 |
gmargin_max | 18.429 |
gxover_max | 5.88124k |
ILOAD | AVG 5.01938 MIN 5.00899 MAX 5.0248 RMS 5.01938 PK2PK 15.8163m |
iload_max | 5.01938 |
ISRC | AVG 317.492m MIN -755.202m MAX 1.15709 RMS 588.07m PK2PK 1.9123 |
min_phase | 50.9788 |
min_phase_freq | 5.88124k |
phase_crossover_freq | 20.5968k |
phase_margin | 50.5732 |
pmargin_max | 50.5732 |
Power(LOAD) | 120.92 |
Power(SRC) | 126.962 |
sw_freq_max | 92.7188k |
VLOAD | AVG 24.0906 MIN 24.0409 MAX 24.1166 RMS 24.0907 PK2PK 75.7137m |
VSRC | AVG 399.968 MIN 399.884 MAX 400.076 RMS 399.968 PK2PK 191.23m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1166) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0409) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (18.429) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (50.5732) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac28_1674.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop28_1640.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop28_1630.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop28_1621.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop28_1635.sxgph |
Other SXGPH Files | |
default#1663#pop | simplis_pop28_1663.sxgph |
Modulator#pop | simplis_pop28_1668.sxgph |