Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Maximum|35% Load |
Date / Time | 12/10/2015 6:11 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\35% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.9988% |
eta_max | 95.9988% |
Frequency(CLK) | 96.5946k |
gain_crossover_freq | 3.88338k |
gain_margin | 28.5551 |
gmargin_max | 28.5551 |
gxover_max | 3.88338k |
ILOAD | AVG 1.75754 MIN 1.75626 MAX 1.75834 RMS 1.75754 PK2PK 2.0785m |
iload_max | 1.75754 |
ISRC | AVG 110.313m MIN -541.715m MAX 634.315m RMS 307.511m PK2PK 1.17603 |
min_phase | 80.7505 |
min_phase_freq | 3.88338k |
phase_crossover_freq | 36.8828k |
phase_margin | 80.6261 |
pmargin_max | 80.6261 |
Power(LOAD) | 42.3505 |
Power(SRC) | 44.1156 |
sw_freq_max | 96.5946k |
VLOAD | AVG 24.0965 MIN 24.0791 MAX 24.1074 RMS 24.0965 PK2PK 28.2785m |
VSRC | AVG 399.989 MIN 399.937 MAX 400.054 RMS 399.989 PK2PK 117.603m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1074) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0791) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (28.5551) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (80.6261) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac21_1254.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop21_1220.sxgph |
SRC
VSRC
ISRC
|
|
SXGPH File | simplis_pop21_1210.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop21_1201.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop21_1215.sxgph |
Other SXGPH Files | |
default#1243#pop | simplis_pop21_1243.sxgph |
Modulator#pop | simplis_pop21_1248.sxgph |