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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|100% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|100% Load
Date / Time 12/10/2015 6:10 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\100% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.2080%
eta_nom 95.2080%
Frequency(CLK) 85.5272k
gain_crossover_freq 4.815k
gain_margin 16.4092
gmargin_nom 16.4092
gxover_nom 4.815k
ILOAD
AVG
5.01757
MIN
5.00715
MAX
5.02378
RMS
5.01757
PK2PK
16.6304m
iload_nom 5.01757
ISRC
AVG
334.08m
MIN
-536.018m
MAX
1.17798
RMS
590.815m
PK2PK
1.714
min_phase 42.6092
min_phase_freq 4.815k
phase_crossover_freq 14.9472k
phase_margin 42.2799
pmargin_nom 42.2799
Power(LOAD) 120.834
Power(SRC) 126.916
sw_freq_nom 85.5272k
VLOAD
AVG
24.0821
MIN
24.0322
MAX
24.1118
RMS
24.0821
PK2PK
79.6067m
VSRC
AVG
379.967
MIN
379.882
MAX
380.054
RMS
379.967
PK2PK
171.4m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1118) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0322) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (16.4092) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (42.2799) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac14_834.sxgph
LOAD
ILOAD
VLOAD
SXGPH File simplis_pop14_800.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop14_790.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop14_781.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop14_795.sxgph
Other SXGPH Files
default#823#pop simplis_pop14_823.sxgph
Modulator#pop simplis_pop14_828.sxgph