| Test Details | |
| Schematic | 8.2_LLC Closed Loop.sxsch | 
| Test | Efficiency and Loop Characterization|Vin Maximum|25% Load | 
| Date / Time | 12/10/2015 6:11 PM | 
| Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\25% Load | 
| Log File | report.txt | 
| Screenshot | schematic.png | 
| Status | PASS | 
| Simulator | simplis | 
| Deck | input.deck | 
| Init | input.deck.init | 
| Measured Scalar Values | |
| Efficiency | 96.0022% | 
| eta_max | 96.0022% | 
| Frequency(CLK) | 97.5208k | 
| gain_crossover_freq | 3.45047k | 
| gain_margin | 30.1637 | 
| gmargin_max | 30.1637 | 
| gxover_max | 3.45047k | 
| ILOAD | AVG 1.25556 MIN 1.2549 MAX 1.25602 RMS 1.25556 PK2PK 1.12133m  | 
				
| iload_max | 1.25556 | 
| ISRC | AVG 78.8057m MIN -501.021m MAX 596.697m RMS 273.119m PK2PK 1.09772  | 
				
| min_phase | 86.516 | 
| min_phase_freq | 3.45047k | 
| phase_crossover_freq | 41.2356k | 
| phase_margin | 86.4619 | 
| pmargin_max | 86.4619 | 
| Power(LOAD) | 30.2549 | 
| Power(SRC) | 31.5148 | 
| sw_freq_max | 97.5208k | 
| VLOAD | AVG 24.0968 MIN 24.0845 MAX 24.1057 RMS 24.0968 PK2PK 21.2617m  | 
				
| VSRC | AVG 399.992 MIN 399.94 MAX 400.05 RMS 399.992 PK2PK 109.772m  | 
				
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (24.1057) is less than or equal to Max. Output1 Voltage Spec (25.2) | 
| Min_VLOAD | PASS: Min. Output1 Voltage (24.0845) is greater than or equal to Min. Output1 Voltage Spec (22.8) | 
| min_gain_margin | PASS: Gain Margin (30.1637) is greater than Min. Gain Margin (12) | 
| min_phase_margin | PASS: Phase Margin (86.4619) is greater than Min. Phase Margin (35) | 
						![]() Bode Plot 
								GAIN 
								PHASE 
							 | 
				|
| SXGPH File | simplis_ac19_1134.sxgph | 
						![]() LOAD 
								ILOAD 
								VLOAD 
							 | 
				|
| SXGPH File | simplis_pop19_1100.sxgph | 
						![]() SRC 
								VSRC 
								ISRC 
							 | 
				|
| SXGPH File | simplis_pop19_1090.sxgph | 
						![]() Primary 
								IDQ1 
								IDQ2 
								Im 
								Ip 
								Ir 
								VSW 
							 | 
				|
| SXGPH File | simplis_pop19_1081.sxgph | 
						![]() Secondary 
								CLK 
								ICout 
								Is1 
								Is2 
								Vs 
							 | 
				|
| SXGPH File | simplis_pop19_1095.sxgph | 
| Other SXGPH Files | |
| default#1123#pop | simplis_pop19_1123.sxgph | 
| Modulator#pop | simplis_pop19_1128.sxgph |