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» DVM Test Report: VOUT=0.6V|Bode Plot|Vin Maximum|100% Load
| Test Details | |
| Schematic | 6.3_LTC3406B - DVM ADVANCED.sxsch |
| Test | VOUT=0.6V|Bode Plot|Vin Maximum|100% Load |
| Date / Time | 12/10/2015 5:52 PM |
| Report Directory | suppress_spec_gen\VOUT=0.6V\BodePlot\Vin Maximum\100% Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | FAIL |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 65.2962% |
| Frequency(CLK) | 955.688k |
| gain_crossover_freq | 18.3383k |
| gain_margin | 33.7095 |
| ILOAD | AVG 603.439m MIN 600.632m MAX 605.224m RMS 603.441m PK2PK 4.59272m |
| ISRC | AVG 101.745m MIN 465.682u MAX 831.192m RMS 254.453m PK2PK 830.727m |
| min_phase | 54.3004 |
| min_phase_freq | 18.3383k |
| phase_crossover_freq | 346.054k |
| phase_margin | 54.2129 |
| Power(LOAD) | 365.354m |
| Power(SRC) | 559.533m |
| VLOAD | AVG 605.449m MIN 602.632m MAX 607.24m RMS 605.451m PK2PK 4.608m |
| VSRC | AVG 5.4999 MIN 5.49917 MAX 5.5 RMS 5.4999 PK2PK 830.727u |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (607.24m) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
| Min_VLOAD | FAIL: Min. Output1 Voltage (602.632m) is not greater than or equal to Min. Output1 Voltage Spec (1.42975) |
| min_gain_margin | PASS: Gain Margin (33.7095) is greater than Min. Gain Margin (12) |
| min_phase_margin | PASS: Phase Margin (54.2129) is greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac5_239.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop6_222.sxgph |
 SRC
VSRC
ISRC
|
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| SXGPH File | simplis_pop6_212.sxgph |
 default
CLK
ILOUT
SW
VOUT
|
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| SXGPH File | simplis_pop6_217.sxgph |
| Other SXGPH Files | |
| clock#pop | simplis_pop6_204.sxgph |
