OpenVerilogA

Opens a Verilog-A source file in the text editor. This will apply syntax highlighting for the Verilog-A language.

OpenVerilogA <filename>

/encoding	encoding. For details see documentation of second argument to LoadFile
/fws	File watcher status, enable\|disable\|auto
filename	Path of Verilog-A source file to open

OpenNetlist to open a model file or netlist file
OpenBasicTextEditor to open a plain text file
OpenScript to open a script
OpenLogicDefinitionEditor to open a logic definition file for the abritrary logic block
OpenVerilogHDL to open a Verilog-HDL source file
OpenAsciiFile to open a schematic file in the text editor

▲ Command Summary ▲
◄ OpenSimplisStatusBox		OpenVerilogHDL ▶