SIMPLIS Parts

Shift Register (Right) with both Async and Sync Set/Reset

The Shift Register (Right) with both Async and Sync Set/Reset models a combination of a clocked data type register and a shift register with right shifts only. The clock edge for the register can be set with the Trigger Condition parameter to be a rising edge (0_TO_1) or a falling edge (1_TO_0). both asynchronous and synchronous set and reset inputs are provided. The active logic level of the inputs can be configured with the Set/Reset Level and Load/Shift Level parameters.

For the right shift register with either asynchronous or synchronous set and reset inputs, see Shift Register (Right).

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Model Name:

Shift Register (Right) with both Async and Sync Set/Reset

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector
Menu Location:

Digital Functions | Registers

Symbol Library:

None - the symbol is automatically generated when placed or edited.

Model File:

None - the device model is generated before simulation.

Subcircuit Name:

  • SIMPLIS_DIGI1_D_SHIFT_REG_RIGHT_N: With Ground Reference
  • SIMPLIS_DIGI1_D_SHIFT_REG_RIGHT_Y: With Ground Reference

Symbol:

Multiple Selections:

Only one device at a time can be edited.

Editing the Shift Register (Right) with both Async and Sync Set/Reset

To configure the right shift register with both async and sync set/reset, follow these steps:

  1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Shift Register (Right) with both Async and Sync Set/Reset Parameters
Label Parameter Description

Clock to Output Delay

Delay from the triggering edge of the clock until the shift register output changes

Number of Bits

Number of input and output bits for the shift register

Trigger Condition

Determines the triggering condition of the shift register clock pin:

  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered

Ground Ref

Determines whether or not a device has a ground reference pin.

Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually ground on the schematic. For more information on the use of Ground Ref for digital components, see When is Ground Ref Required?

Minimum Clock Width

Minimum valid clock width. Clock widths less than this parameter will not trigger the shift register.

Setup Time

Minimum time that input signals must remain constant before the triggering clock edge in order to register as a valid change in the inputs

Hold Time

Minimum time that input signals must remain constant after the triggering clock edge in order to register as a valid change in the inputs

Initial Condition

Initial condition of the shift register output in decimal

Load/Shift Level

Determines the logic level of the shift register load/shift (LD/SH) pin:

  • Load_0/Shift_1 means load on low and shift on high.
  • Load_1/Shift_0 means load on high and shift on low.

To define the set/reset behavior of the shift register, follow these steps from the Shift Register (Right) with both Async and Sync Set/Reset dialog box:

  1. Click on the   Set/Reset   tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Shift Register (Right) with both Async and Sync Set/Reset Set/Reset Parameters
Label Parameter Description

Set/Reset Level

Determines the set/reset level of a device:

  • 1 means active high
  • 0 means active low

Asynchronous Set/Reset Parameters

Set To

Determines the shift register output value when the asynchronous set pin goes active

Reset To

Determines the shift register output value when the asynchronous reset pin goes active

Set/Reset Delay

Delay from when the set or reset pin goes active until the output is actually set or reset

Synchronous Set/Reset Parameters

Set To

Determines the shift register output value when the synchronous set pin goes active

Reset To

Determines the shift register output value when the synchronous reset pin goes active

To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps from the Shift Register (Right) with both Async and Sync Set/Reset dialog box:

  1. Click on the   Interface   tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Shift Register (Right) with both Async and Sync Set/Reset Interface Parameters
Label Parameter Description

Input Resistance

Input resistance of each input pin

Threshold

Hysteresis

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Register input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :
Input Logic Transition Actual Threshold
0 ➞ 1 TH = Threshold + 0.5 * Hysteresis
1 ➞ 0 TL = Threshold - 0.5 * Hysteresis
 

Output Resistance

Output resistance of the shift register output pins

Output High Voltage

Output high voltage for the shift register output pins

Output Low Voltage

Output low voltage for the shift register output pins

Truth Table

The following truth table assumes these parameter values:

When the EN input is high and the Load/Shift Level=Load_1/Shift_0, the register will load the D input when the LD/SH pin is high and shift the Q output when the LD/SH pin is low.

Inputs

Output

Action

LD/SH

SET

RST

ASET

ARST

EN

D

CLK

Q

0 or 1

0

0

0

0

0

0 or 1

Last Q

Retain state

1

0

0

0

0

1

0 or 1

Data input

Load data

0

0

0

0

0

1

0

Q = Last Q shifted right, MSB=0

Shift left

0

0

0

0

0

1

1

Q = Last Q shifted right, MSB=1

Shift left

0 or 1

1

0

0

0

0 or 1

0 or 1

Synchronous Set To value

Synchronous set

0 or 1

0

1

0

0

0 or 1

0 or 1

Synchronous Reset To value

Synchronous reset

0 or 1

0 or 1

0 or 1

1

0

0 or 1

0 or 1

0 or 1

Asynchronous Set To value

Asynchronous set

0 or 1

0 or 1

0 or 1

0

1

0 or 1

0 or 1

0 or 1

Asynchronous Reset To value

Asynchronous reset

0 or 1

1

1

0

0

0 or 1

0 or 1

Last Q

Illegal concurrent SET and RST

0 or 1

0 or 1

0 or 1

1

1

0 or 1

0 or 1

0 or 1

Last Q

Illegal concurrent ASET and ARST

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_047_shiftregisterright_example.zip.

To simulate this design, follow these steps:

  1. Unzip the archive to a location on your computer.
  2. To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

This example of the shift register (right) with both async and sync set/reset uses two Digital Signal Sources to generate the input pulses to the shift register (right) with both async and sync set/reset. The input source waveforms are defined in a text file with each state transition defined on a single line. These two sources excite every state transition in the truth table.

For clarity, the simulation waveforms taken from the circuit example have been divided into three sections.

Load and Shift operations when D=0: 0-1us

The image below shows the Load and Shift behavior when the D input is 0. For a Right shift the D input is shifted into the MSB, and since D=0, the new Q output is half the old Q. The initial condition of the Shift Register (Right) with both Async and Sync Set/Reset is set to 15 decimal in the example.

Load and Shift with D=0
Time Event Q Output

100n

 Load

10

200n

 Retain state

10

300n

 Shift right

5

400n

 Shift right

2

500n

 Shift right

1

600n

 Shift right

0

700n

 Shift right

0

800n

 Shift right

0

Load and Shift operations when D=1: 1-2us

The image below shows the Load and Shift behavior when the D input is 1. For a Right shift the D input is shifted into the MSB, adding 2n-1 to the result. For this example, n=4, so the MSB is equal to 8.

Load and Shift with D=1
Time Event Q Output

1.1u

 Load

4

1.2u

 Retain state

4

1.3u

 Shift right

10

1.4u

 Shift right

13

1.5u

 Shift right

14

1.6u

 Shift right

15

1.7u

 Shift right

15

1.8u

 Shift right

15

Asynchronous and Synchronous Set/Reset: 2-3us

The image below shows the set/reset behavior of the Register.

Asynchronous and Synchronous Set/Reset
Time Event Q Output

2.1u

 Synchronous set

9

2.2u

 Synchronous reset

2

2.3u

 Load

7

2.4u

 Illegal concurrent SET and RST

7

2.52u

 Asynchronous set

11

2.62u

 Asynchronous reset

1

2.7u

 Load

7

2.82u

 Illegal concurrent ASET and ARST

7

Subcircuit Parameters

Because the shift register (right) with both async and sync set/reset model is generated by a template script when the simulation is executed, a fixed model cannot be inserted into a netlist. The template script for this device is simplis_make_register_model.sxscr, which you, as a licensed user, can download in a zip archive of all built-in scripts.

To download this zip file, follow these steps:

Note: You will be prompted to log in with the user name and password given to you when you registered.

  1. Click here to go to the product-installation page on the SIMetrix website.
  2. Click Download Links in the first paragraph of the product-installation web page.
  3. Scroll down to the Built-in Scripts section.
  4. Right click on Download and select Save target as..., and then navigate to a location on your computer to save the zip file.