SIMPLIS Parts

SIMPLIS JFET Models

Any SPICE JFET model installed in the SIMetrix library can be converted for use in SIMPLIS. When a JFET is placed on a SIMPLIS schematic, a model parameter extraction routine is invoked to automatically convert the SPICE model to a SIMPLIS model. During the model parameter extraction process, SIMetrix/SIMPLIS automatically runs several SPICE simulations on the SPICE model and extracts the SIMPLIS model parameters. After the Piecewise Linear (PWL) model parameters have been extracted, the resulting JFET model will run in SIMPLIS.

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Extracting the JFET Parameters

When you place a JFET symbol on a schematic, the Extract JFET Parameters dialog opens for you to edit the default test conditions. You should change the test conditions to accurately reflect the expected voltage, the current, and the temperature of the device in your circuit.

The default test conditions are defined using the command shell menu, File ▶ Options ▶ SIMPLIS Options.... For additional information, see SIMPLIS JFET Options.

The following table describes the Extract JFET Parameters dialog test conditions.

SIMPLIS JFET Model Levels

The SIMPLIS JFET models have multiple levels to balance simulation speed vs. model accuracy. There are currently four levels: 0, 1, 2, and 3. As the model level increases, so does the model complexity and, as a rule, simulation times also increase.

SIMPLIS extracts a model based on the model level chosen in the Extract JFET Parameters dialog. Currently model levels 0, 1, and 2 are supported by the model parameter extraction algorithms. The level 3 model is intended for more detailed modeling and can be manually generated from a device datasheet or from a spreadsheet or other program. For details of the Level 3 model, see Manually Generate and Customize JFET Models. Although these models are internally saved as ASCII text, the following illustrations show the three model levels in a schematic form.

Level 0 Model

Level 0 models a switch with on/off resistance values, body diode, and gate capacitance. The Level 0 Model can be used  for AC Bode Plots and for simulating output voltage during load and line transients when the actual switching waveform shapes are not critical.

• The conduction region is modeled with an on and off resistance.
• CGS capacitance is modeled with a linear capacitor and has a parallel 10Meg resistor.
• Gate resistance is modeled with RG.
• The body diode is modeled with a 2- or 3-segment resistor; the number of segments is specified in the SIMPLIS Options dialog.
• There is no output (CDS) or reverse capacitance (CDG).

Below is a schematic view of a Level 0 model:

Level 0 models these circuit elements	Level 0 Schematic
QQ1: Ideal Switch with On and Off Resistance CGS: Linear Capacitance RGS: 10Meg W Resistor RG: Internal Gate Resistor

Level 1 Model

Level 1 models a switch with on/off resistance values, body diode, and gate capacitance, plus a lumped-linear Coss capacitance across drain and source terminals. The Level 1 Model can be used for power stage simulations, including Quasi-resonant, LLC, and phase-shifted bridge topologies,as well as for AC Bode Plots and for simulating output voltage during load and line transient.

• The conduction region is modeled with an on and off resistance.
• CGS capacitance is modeled with a linear capacitor and has a parallel 10Meg resistor.
• Gate resistance is modeled with RG.
• The body diode is modeled with a 2- or 3-segment resistor; the number of segments is specified in the SIMPLIS Options dialog.
• There is no reverse capacitance (CDG).
• The bulk COSS capacitor is the parallel CDG and CDS capacitors with the value as follows:
  COSS = (QCDS1 - QCDS0)/(VCDS1 - VCDS0).

Below is a schematic view of a Level 1 model:

Level 1 models these circuit elements	Level 1 Schematic
QQ1: Switch with On and Off Resistance CGS: Linear Capacitance RGS: 10Meg W Resistor RG: Internal Gate Resistor

Level 2 Model

Level 2 models a switch with forward transconductance gain, a body diode, and gate capacitance, plus a nonlinear Gate-Drain, Drain-Source, and Gate-Source capacitors. The active region is modeled by a linear transconductance gain (ID is proportional to VGS - VT0). The Level 2 Model can be used for switching losses, JFET voltage and current stresses, and all simulations covered by Level 0 and Level 1 models.

• Forward conduction is modeled with a two-segment gain. The following gain information assumes that the device is being switched from an off state to an on state:
• • Below the threshold voltage (VT0 - HYSTWD/2), the gain is 0.
  • Above the threshold, the gain is
    GAIN = ID2/(VGS2 - VT0 - HYSTWD/2) units: A/V (transconductance)
• Gate resistance is modeled with RG.
• The body diode is modeled with a 2- or 3-segment resistor; the number of segments is specified in the SIMPLIS Options dialog.
• This model level implements non-linear capacitors for all three capacitors (CGS , CDG and CDS). The Model Extraction algorithms determine the number of segments for each capacitor. Typically the Gate-Source capacitor is linear, while the Drain-Gate and Drain-Source capacitors have four segments.
  The actual capacitor used is determined by the CGS_NSEG , CDG_NSEG and CDS_NSEG parameters.
• • If one of these parameters is set to 0, the capacitor at that  location will be an open circuit.
  • If the number of segments is set to 1, a linear capacitor is implemented with capacitance:
    Cxx = (Qxx1 - Qxx0)/(Vxx1 - Vxx0)
    where "xx" is the capacitor GS, DG, or DS.
  • Otherwise, if the CXX_NSEG parameter is set to a value greater than 1, the capacitor is implemented with a PWL capacitor. For more information, see JFET Model Parameters section below.

Below is a schematic view of Level 2 model:

Level 2 models these circuit elements	Level 2 Schematic
QQ1: Switch with forward transconductance RG: Internal Gate Resistor CGS: PWL Capacitance RGS: 10Meg W Resistor CDG: PWL capacitance CDS: PWL capacitance

Level 3 Model

The Level 3 model extends the Level 2 model to include up to 5 forward transconductance gain segments. The Level 3 model can be used to more accurately model converter losses, and converters which operate over a wide range of currents.

Note: The model extraction algorithms do not extract a level 3 model. The level 3 model is available for manually generated models. See Manually Generate and Customize JFET Models for details.

• The level 3 model is the same as the Level 2 model but the Forward Conduction is modeled with a variable number of PWL segments.
• As with the Level 2 model, the first segment has a gain of 0.
• The second segment has a gain of
  GAIN2 = ID2/(VGS2 - VT0)  units: A/V (transconductance)
• Further segments have gain values which are defined by the slopes between successive point pairs.
  For example, the third segment has a gain of
  GAIN3 = (ID3 - ID2)/(VGS3 - VGS2) units: A/V (transconductance)
• Up to five segments of gain can be used with this model. The number of gain segments is controlled by the GAIN_NSEG parameter.

Below is a schematic view of a Level 3 Model:

Level 3 models these circuit elements	Level 3 Schematic
QQ1: Switch with forward transconductance RG: Internal Gate Resistor CGS: PWL Capacitance RGS: 10Meg W Resistor CDG: PWL capacitance CDS: PWL capacitance !R_GAIN: PWL forward transconductance gain G1: Converts gate-source voltage to a current

User-defined Models

The user-defined model uses parameters entered directly in the Edit JFET Parameters dialog without invoking the model extraction algorithms. A JFET can be switched from an extracted model to a user-defined model at any point; however the extracted parameters are by default copied over to the user-defined parameters, replacing any user-entered values. You can disable this behavior in the SIMPLIS Options dialog by clearing the check box labeled "Automatically copy extracted parameters to User-defined parameters." You can access these options from the command shell menu File ▶ Options ▶ SIMPLIS Options.... For more information, see SIMPLIS JFET Options.

The following table describes the Edit JFET Parameters entries.

User-defined model schematic

Models these circuit elements	User-defined Schematic
QQ1: Switch with On and Off Resistance CGS: Linear Input Capacitance RGS: 10Meg W resistor RG: Internal Gate Resistor COSS: Lumped-linear output capacitance

Customize or Manually Generate JFET Models

You can customize or manually generate your own JFET models using a parameter string with multiple PARAM_NAME=PARAM_VALUE key-value pairs. The parameter names and their functions are described in the JFET Model Parameters section below. You can interpret the SIMPLIS parameter values from device datasheet specifications and curves.

You can compose the parameter string in a text editor, spreadsheet, or script. The order of the parameter names in the parameter string and the capitalization of the parameter names are irrelevant.

You can include a PROTECTED=1 key-value pair to prevent from extracting a model and overwriting your manually generated parameters. The PROTECTED=1 key-value pair is not used in the simulation.  

Note: When you click on the device after adding the PROTECTED=1 key-value pair, the following message box appears to warn you that this is a hand-edited model.

To customize or generate your own JFET model, follow these steps:

1. Create a parameter string of multiple PARAM_NAME=PARAM_VALUE key-value pairs using your preferred text editor, spreadsheet or script.
2. Add the PROTECTED=1 key-value pair to the parameter string.
3. Extract a JFET model and place it on a schematic.
4. Right click on the symbol and select Edit/Add Properties....
5. Double click on the PARAM_VALUES property.
   The Edit Property dialog opens. At this point, you can change individual parameters in the Value box, or replace the entire default properties with the parameter string that you created in Step 2.
6. To replace the entire string, follow these steps:
   1. Click in the Value box and type Ctrl A to select all of the existing parameter string, and press Delete.
   2. Copy the parameter string you completed in Step 2 and paste into the Value box.
   3. Click Ok.
7. To change the name of your customized model, double click the VALUE property in the Edit Properties dialog, and change the name in the Value box.
8. To return to the schematic, click Ok.

JFET Model Parameters

The following tables detail the parameters which define the electrical behavior of the JFET model. Several other parameters in the PARAM_VALUES property have no effect on the electrical behavior of the model. These parameters are used to populate the Extract JFET Parameters dialog box.

Note: The default values are unlikely to appear in an extracted model. If these parameter values appear in your design, there has been an error in composing the parameter string.

Capacitor Model

Capacitors are modeled in SIMPLIS with Piecewise Linear capacitors.

• A system of point-pairs is used with the X-Y plane defined with Voltage on the X-axis and Charge on the Y-axis.
• A system of subscripts is used to define the point pairs. For example, VCDS0 and QCDS0 represent the lowest Voltage-Charge pair for the CDS capacitor with increasing subscripts representing increasing VDS voltages.
• On the Voltage-Charge plane, the capacitance is the slope of any segment.
• The actual number of segments is controlled by the CXX_NSEG, where "xx" is the capacitor GS, DG, or DS. The model uses only the number of point-pairs defined by CXX_NSEG; higher numbered point-pairs ignored.

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