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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|40% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|40% Load
Date / Time 12/10/2015 6:15 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\40% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.7939%
eta_min 95.7939%
Frequency(CLK) 79.5724k
gain_crossover_freq 4.8037k
gain_margin 25.1213
gmargin_min 25.1213
gxover_min 4.8037k
ILOAD
AVG
2.00835
MIN
2.00668
MAX
2.00972
RMS
2.00835
PK2PK
3.04782m
iload_min 2.00835
ISRC
AVG
140.356m
MIN
-571.606m
MAX
692.871m
RMS
350.929m
PK2PK
1.26448
min_phase 46.3592
min_phase_freq 4.8037k
phase_crossover_freq 27.9407k
phase_margin 46.1121
pmargin_min 46.1121
Power(LOAD) 48.3912
Power(SRC) 50.5159
sw_freq_min 79.5724k
VLOAD
AVG
24.0949
MIN
24.075
MAX
24.1112
RMS
24.0949
PK2PK
36.2586m
VSRC
AVG
359.986
MIN
359.931
MAX
360.057
RMS
359.986
PK2PK
126.448m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1112) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.075) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (25.1213) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (46.1121) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac36_2154.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop36_2120.sxgph
SRC
ISRC
VSRC
SXGPH File simplis_pop36_2110.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop36_2101.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop36_2115.sxgph
Other SXGPH Files
default#2143#pop simplis_pop36_2143.sxgph
Modulator#pop simplis_pop36_2148.sxgph