Test Details | |
Schematic | LTC3406B - DVM ADVANCED.sxsch |
Test | Ac Analysis|Bode Plot|Vin Minimum|50% Load |
Date / Time | 12/10/2015 5:40 PM |
Report Directory | dc_dc_built_in\AcAnalysis\Bode Plot\Vin Minimum\50% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 79.2658% |
gain_crossover_freq | 23.6955k |
gain_margin | 26.539 |
ILOAD1 | AVG 750.292m MIN 748.501m MAX 751.897m RMS 750.293m PK2PK 3.39604m |
ISRC1 | AVG 316.747m MIN 381.114u MAX 1.01266 RMS 498.933m PK2PK 1.01228 |
min_phase | 40.2817 |
min_phase_freq | 23.6955k |
phase_crossover_freq | 419.274k |
phase_margin | 40.2308 |
Power(LOAD1) | 1.12963 |
Power(SRC1) | 1.42511 |
sw_freq | 955.649k |
VLOAD1 | AVG 1.50558 MIN 1.50199 MAX 1.5088 RMS 1.50558 PK2PK 6.8147m |
VSRC1 | AVG 4.49968 MIN 4.49899 MAX 4.5 RMS 4.49968 PK2PK 1.01228m |
Measured Spec Values | |
Max_VLOAD1 | PASS: Max. Output1 Voltage (1.5088) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
Min_VLOAD1 | PASS: Min. Output1 Voltage (1.50199) is greater than or equal to Min. Output1 Voltage Spec (1.42975) |
min_gain_margin | PASS: Gain Margin (26.539) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (40.2308) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac5_209.sxgph |
LOAD1
ILOAD1
VLOAD1
|
|
SXGPH File | simplis_pop5_195.sxgph |
SRC1
VSRC1
ISRC1
|
|
SXGPH File | simplis_pop5_190.sxgph |
default
FREQUENCY
|
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SXGPH File | simplis_pop5_173.sxgph |
Other SXGPH Files | |
clock#pop | simplis_pop5_178.sxgph |