Test Details | |
Schematic | LTC3406B - DVM ADVANCED.sxsch |
Test | Ac Analysis|Bode Plot|Vin Nominal|50% Load |
Date / Time | 12/10/2015 5:39 PM |
Report Directory | dc_dc_built_in\AcAnalysis\Bode Plot\Vin Nominal\50% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 79.1235% |
gain_crossover_freq | 23.5062k |
gain_margin | 28.1964 |
ILOAD1 | AVG 750.315m MIN 748.345m MAX 751.985m RMS 750.316m PK2PK 3.63996m |
ISRC1 | AVG 285.599m MIN 423.431u MAX 1.03248 RMS 475.287m PK2PK 1.03206 |
min_phase | 40.5937 |
min_phase_freq | 23.5062k |
phase_crossover_freq | 401.216k |
phase_margin | 40.5382 |
Power(LOAD1) | 1.1297 |
Power(SRC1) | 1.42777 |
sw_freq | 955.649k |
VLOAD1 | AVG 1.50563 MIN 1.50168 MAX 1.50898 RMS 1.50563 PK2PK 7.30416m |
VSRC1 | AVG 4.99971 MIN 4.99897 MAX 5 RMS 4.99971 PK2PK 1.03206m |
Measured Spec Values | |
Max_VLOAD1 | PASS: Max. Output1 Voltage (1.50898) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
Min_VLOAD1 | PASS: Min. Output1 Voltage (1.50168) is greater than or equal to Min. Output1 Voltage Spec (1.42975) |
min_gain_margin | PASS: Gain Margin (28.1964) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (40.5382) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
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SXGPH File | simplis_ac2_80.sxgph |
LOAD1
VLOAD1
ILOAD1
|
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SXGPH File | simplis_pop2_66.sxgph |
SRC1
VSRC1
ISRC1
|
|
SXGPH File | simplis_pop2_61.sxgph |
default
FREQUENCY
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SXGPH File | simplis_pop2_44.sxgph |
Other SXGPH Files | |
clock#pop | simplis_pop2_49.sxgph |