MOSFET

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Note

Level 1, 2, 3 and 17 MOSFETs are described in this section. For other devices:

• BSIM3
• BSIM4
• HiSim HV
• PSP
• MOS9, MOS11 and other NXP devices see NXP Compact Models

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NMOS Model Syntax

PMOS Model Syntax

MOS Levels 1, 2 and 3: Model Parameters

CJ Default

If not specified CJ defaults to \[ \sqrt{\epsilon_sq\times\text{NSUB}\times1\text{e}6 / (2\times\text{PB})} \] where

• $\epsilon_s$ = 1.03594314e-10 (permittivity of silicon)
• q = 1.6021918e-19 (electronic charge)
• NSUB, PB model parameters

Notes for levels 1, 2 and 3:

The three levels 1 to 3 are as follows:

The above models differ from all other SIMetrix (and SPICE) models in that they contain many geometry relative parameters. The geometry of the device (length, width etc.) is entered on a per component basis and various electrical characteristics are calculated from parameters which are scaled according to those dimensions. This is approach is very much geared towards integrated circuit simulation and is inconvenient for discrete devices. If you are modelling a particular device by hand we recommend you use the level 17 model which is designed for discrete vertical devices.

MOS Level 17: Model Parameters

Notes for level 17

In SIMetrix version 5.2 and earlier, this model used a level parameter value of 7 instead of the current 17. The number was changed so that a PSpice compatible BSIM3 model (level=7) could be offered. In order to retain backward compatibility, any level 7 model containing the parameters cgdmax, cgdmin, xg1cgd, xg2cgd or vtcgd will automatically be switched to level=17.

The level 17 MOSFET was developed to model discrete vertical MOS transistors rather than the integrated lateral devices that levels 1 to 3 are aimed at. Level 17 is based on level 1 but has the following important additions and changes:

• New parameters to model gate-drain capacitance
• 2 new parameters to model rdson variation with temperature.
• All parameters are absolute rather than geometry relative. (e.g. capacitance is specified in farads not farads/meter)

Gate-drain capacitance equation:

\[ \begin{split} C_{gd} = \left(0.5 - \frac{1}{\pi}\tan^{-1}\left(\left(\text{VTCGD} - v\right) - \text{XG1CGD}\right)\right)\text{CGDMIN} \\ + \left(0.5 - \frac{1}{\pi}\tan^{-1}\left(\left(\text{VTCGD} - v\right)\text{XG2CGD}\right)\right)\text{CGDMAX} \end{split} \]

where $v$ is the gate-drain voltage. This is an empirical formula devised to fit measured characteristics. Despite this it has been found to follow actual measured capacitance to remarkable accuracy.

To model gate-drain capacitance quickly and to acceptable accuracy set the five $\text{C}_{\text{gd}}$ parameters as follows:

1. Set CGDMIN to minimum possible value of $\text{C}_{\text{gd}}$ i.e. when device is off and drain voltage at maximum.
2. Set CGDMAX to maximum value of $\text{C}_{\text{gd}}$ i.e. when device is on with drain-source voltage low and gate-source voltage high. If this value is not known use twice the value of $\text{C}_{\text{gd}}$ for $\text{V}_{\text{gd}}=0$.
3. Set XG2CGD to 0.5, XG1CGD to 0.1 and leave VTCGD at default of 0.