SIMPLIS Parts

Data Register

The Data Register models a clocked data register with a load (enable) input. The clock edge for the register can be set with the Trigger Condition parameter to be a rising edge (0_TO_1) or a falling edge (1_TO_0). The set/reset events can be configured to be asynchronous or synchronous to the clock with the Set/Reset Type parameter. The active logic levels of the inputs can be configured with the Set/Reset Level and Load Level parameters.

For the data register with both asynchronous and synchronous set and reset inputs, see Data Register with both Async and Sync Set/Reset.

Related topics:

In this Topic ShowHide

Editing the Data Register
Truth Table
- Asynchronous Set/Reset
- Synchronous Set/Reset
Examples
Waveforms
Subcircuit Parameters

Model Name:	Data Register
Simulator:		This device is compatible with the SIMPLIS simulator.
Parts Selector Menu Location:	Digital Functions \| Registers
Symbol Library:	None - the symbol is automatically generated when placed or edited.
Model File:	None - the device model is generated before simulation.
Subcircuit Name:	SIMPLIS_DIGI1_D_DATA_REG_SOAS_N: With Ground Reference SIMPLIS_DIGI1_D_DATA_REG_SOAS_Y: With Ground Reference
Symbol:
Multiple Selections:	Only one device at a time can be edited.

Editing the Data Register

To configure the data register, follow these steps:

Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
Make the appropriate changes to the fields described in the table below the image.

Label	Parameter Description
Clock to Output Delay	Delay from the triggering edge of the clock until the data register output changes
Number of Bits	Number of input and output bits for the data register
Trigger Condition	Determines the triggering condition of the data register clock pin: 0_TO_1 for rising edge triggered 1_TO_0 for falling edge triggered
Ground Ref	Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually ground on the schematic. For more information on the use of Ground Ref for digital components, see When is Ground Ref Required?
Minimum Clock Width	Minimum valid clock width. Clock widths less than this parameter will not trigger the data register.
Setup Time	Minimum time that input signals must remain constant before the triggering clock edge in order to register as a valid change in the inputs
Hold Time	Minimum time that input signals must remain constant after the triggering clock edge in order to register as a valid change in the inputs
Initial Condition	Initial condition of the data register output in decimal
Load Level	Determines the logic level of the shift register load (LOAD) pin: 0 means load on low. 1 means load on high

To define the set/reset behavior of the data register, follow these steps from the Data Register dialog box:

Click on the Set/Reset tab.
Make the appropriate changes to the fields described in the table below the image.

Label

Parameter Description

Set/Reset Delay

Delay from when the set or reset pin goes active until the output is actually set or reset. The Set/Reset Delay is used only for asynchronous set/reset. Registers with synchronous set/reset use the Clock to Output Delay.

Set/Reset Level

Determines the set/reset level of a device:

1 means active high
0 means active low

Set/Reset Type

Determines whether or not output events are synchronized with a clock event:

Set/Reset Type	Set/Reset Behavior
SYNC	Set/Reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNC	Set/Reset events are asynchronous to the clock edge.

Set To

Determines the data register output value when the set pin goes active

Reset To

Determines the data register output value when the reset pin goes active

To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps from the Data Register dialog box:

Click on the Interface tab.
Make the appropriate changes to the fields described in the table below the image.

Label

Parameter Description

Input Resistance

Input resistance of each input pin

Threshold

Hysteresis

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Register input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :

Input Logic Transition	Actual Threshold
0 ➞ 1	TH = Threshold + 0.5 * Hysteresis
1 ➞ 0	TL = Threshold - 0.5 * Hysteresis

Output Resistance

Output resistance of the data register output pins

Output High Voltage

Output high voltage for the data register output pins

Output Low Voltage

Output low voltage for the data register output pins

Truth Table

The two truth tables below show the logic behavior with asynchronous and synchronous set/reset.

Asynchronous Set/Reset

The following truth table assumes these parameter values:

Set/Reset Type=SYNC
Trigger Condition=0_TO_1 which represents a rising edge clocked data register
Set/Reset level=1
Load Level=1.

Inputs				Output	Action
LOAD	ASET	ARST	CLK	Q	Action
0	0	0		Last Q	Retain state
1	0	0		Data input	Load data
0 or 1	1	0	0 or 1	Asynchronous Set To value	Asynchronous set
0 or 1	0	1	0 or 1	Asynchronous Reset To value	Asynchronous reset
0 or 1	1	1	0 or 1	Last Q	Illegal concurrent ASET and ARST

Synchronous Set/Reset

The following truth table assumes these parameter values:

Set/Reset Type=SYNC
Trigger Condition=0_TO_1 which represents a rising edge clocked data register
Set/Reset level=1
Load Level=1.

Inputs				Output	Action
LOAD	SET	RST	CLK	Q	Action
0	0	0		Last Q	Retain state
1	0	0		Data input	Load data
0 or 1	1	0		Synchronous Set To value	Synchronous set
0 or 1	0	1		Synchronous Reset To value	Synchronous reset
0 or 1	1	1		Last Q	Illegal concurrent SET and RST

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_050_dataregistersoas_example.zip.

To simulate this design, follow these steps:

Unzip the archive to a location on your computer.
To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

This example of the data register uses two Digital Signal Sources to generate the input pulses to the data register. The input source waveforms are defined in a text file with each state transition defined on a single line. These two sources excite every state transition in the truth table for asynchronous set/reset.

In the circuit example, the initial condition of the data register is set to 15 decimal. The behavior of the register in response to the inputs on a rising clock edge is described in the following table.

Synchronous events
Time	Event	Q Output
100n	Load	4
200n	Retain state	4
300n	Load	8
400n	Retain state	8
600n	Load	5

The asynchronous set and reset inputs are asserted according to this table:

Asynchronous events
Time	Event	Q Output
420n	Asynchronous set	11
470n	Asynchronous reset	1
675n	Illegal concurrent ASET and ARST	5

The waveforms for the data register show each state change.

Subcircuit Parameters

Because the data register model is generated by a template script when the simulation is executed, a fixed model cannot be inserted into a netlist. The template script for this device is simplis_make_register_model.sxscr, which you, as a licensed user, can download in a zip archive of all built-in scripts.

To download this zip file, follow these steps:

Note: You will be prompted to log in with the user name and password given to you when you registered.

Click here to go to the product-installation page on the SIMetrix website.
Click Download Links in the first paragraph of the product-installation web page.
Scroll down to the Built-in Scripts section.
Right click on Download and select Save target as..., and then navigate to a location on your computer to save the zip file.