SIMPLIS Parts

Shift Register (Multi-bit)

The Shift Register (Multi-bit) models a combination of a clocked data type register and a shift register which can shift multiple bits on a clock edge. When the register is left shifting, the LSBs shifted into the register are controlled by the LFILL pin; during a right shift, the MSBs shifted into the register are controlled by the RFILL pin. The set and reset inputs can be either asynchronous or synchronous, depending on the Set/Reset Type parameter. The active logic level of the inputs can be configured with the Set/Reset Level and Load/Shift Level parameters.

For the multi-bit shift register with either asynchronous or synchronous set and reset inputs, see Shift Register (Multi-bit) with both Async and Sync Set/Reset.

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Model Name:

Shift Register (Multi-bit)

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector
Menu Location:

Digital Functions | Registers

Symbol Library:

None - the symbol is automatically generated when placed or edited.

Model File:

None - the device model is generated before simulation.

Subcircuit Name:

  • SIMPLIS_DIGI1_D_SHIFT_REG_MULTIBIT_N: With Ground Reference
  • SIMPLIS_DIGI1_D_SHIFT_REG_MULTIBIT_Y: With Ground Reference

Symbol:

Multiple Selections:

Only one device at a time can be edited.

Editing the Shift Register (Multi-bit)

To configure the multi-bit shift register, follow these steps:

  1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Shift Register (Multi-bit) Parameters
Label Parameter Description

Clock to Output Delay

Delay from the triggering edge of the clock until the multi-bit shift register output changes

Number of Bits

Number of input and output bits for the multi-bit shift register

Trigger Condition

Determines the triggering condition of the multi-bit shift register clock pin:

  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered

Ground Ref

Determines whether or not a device has a ground reference pin.

Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually ground on the schematic. For more information on the use of Ground Ref for digital components, see When is Ground Ref Required?

Minimum Clock Width

Minimum valid clock width. Clock widths less than this parameter will not trigger the multi-bit shift register.

Setup Time

Minimum time that input signals must remain constant before the triggering clock edge in order to register as a valid change in the inputs

Hold Time

Minimum time that input signals must remain constant after the triggering clock edge in order to register as a valid change in the inputs

Initial Condition

Initial condition of the multi-bit shift register output in decimal

Left/Right Level

Determines the logic level of the multi-bit shift register left/right (L/R) pin:

  • Left_0/Right_1 means shift left on low and shift right on high.
  • Left_1/Right_0 means shift left on high and shift right on low.

Load/Shift Level

Determines the logic level of the multi-bit shift register load/shift (LD/SH) pin:

  • Load_0/Shift_1 means load on low and shift on high.
  • Load_1/Shift_0 means load on high and shift on low.

To define the set/reset behavior of the shift register, follow these steps from the Shift Register (Multi-bit) dialog box:

  1. Click on the   Set/Reset   tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Shift Register (Multi-bit) Set/Reset Parameters
Label Parameter Description

Set/Reset Delay

Delay from when the set or reset pin goes active until the output is actually set or reset. The Set/Reset Delay is used only for asynchronous set/reset. Registers with synchronous set/reset use the Clock to Output Delay.

Set/Reset Level

Determines the set/reset level of a device:

  • 1 means active high
  • 0 means active low

Set/Reset Type

Determines whether or not output events are synchronized with a clock event:

Set/Reset TypeSet/Reset Behavior
SYNCSet/Reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNCSet/Reset events are asynchronous to the clock edge.
 

Set To

Determines the multi-bit shift register output value when the set pin goes active

Reset To

Determines the multi-bit shift register output value when the reset pin goes active

To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps from the Shift Register (Multi-bit) dialog box:

  1. Click on the   Interface   tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Shift Register (Multi-bit) Interface Parameters
Label Parameter Description

Input Resistance

Input resistance of each input pin

Threshold

Hysteresis

The Threshold (T) and Hysteresis (H) of the Schmitt trigger input buffer on each Register input. To determine the low-to-high threshold (TH) and the high-to-low threshold (TL), substitute Threshold (T) and Hysteresis (H) in each of the following formulas :
Input Logic Transition Actual Threshold
0 ➞ 1 TH = Threshold + 0.5 * Hysteresis
1 ➞ 0 TL = Threshold - 0.5 * Hysteresis
 

Output Resistance

Output resistance of the multi-bit shift register output pins

Output High Voltage

Output high voltage for the multi-bit shift register output pins

Output Low Voltage

Output low voltage for the multi-bit shift register output pins

Truth Table

The two truth tables below show the logic behavior with asynchronous and synchronous set/reset.

Asynchronous Set/Reset

The following truth table assumes these parameter values:

When the EN input is high, and the Load/Shift Level=Load_1/Shift_0, the register will load the D input when the LD/SH pin is high, and shift the Q output when the LD/SH pin is low.

Inputs

Output

Action

LD/SH

SET

RST

EN

L/R

LFILL

RFILL

CLK

Q

0 or 1

0

0

0

0 or 1

0 or 1

0 or 1

Last Q

Retain state

1

0

0

1

0 or 1

0 or 1

0 or 1

Data input

Load data

0

0

0

1

0

0

0 or 1

Q = Last Q shifted left SC bits, fill LSBs with 0's.

Shift left

0

0

0

1

1

0 or 1

0

Q = Last Q shifted right, fill MSBs with 0's.

Shift Right

0

0

0

1

0

1

0 or 1

Q = Last Q shifted left, fill LSBs with 1's.

Shift left

0

0

0

1

1

0 or 1

1

Q = Last Q shifted right, fill MSBs with 1's.

Shift Right

0 or 1

1

0

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

Asynchronous Set To value

Asynchronous set

0 or 1

0

1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

Asynchronous Reset To value

Asynchronous reset

0 or 1

1

1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

Last Q

Illegal concurrent ASET and ARST

Synchronous Set/Reset

The following truth table assumes these parameter values:

When the EN input is high and the Load/Shift Level=Load_1/Shift_0, the register will load the D input when the LD/SH pin is high and shift the Q output when the LD/SH pin is low.

Inputs

Output

Action

LD/SH

SET

RST

EN

L/R

LFILL

RFILL

CLK

Q

0 or 1

0

0

0

0 or 1

0 or 1

0 or 1

Last Q

Retain state

1

0

0

1

0 or 1

0 or 1

0 or 1

Data input

Load data

0

0

0

1

0

0

0 or 1

Q = Last Q shifted left SC bits, fill LSBs with 0's.

Shift left

0

0

0

1

1

0 or 1

0

Q = Last Q shifted right, fill MSBs with 0's.

Shift Right

0

0

0

1

0

1

0 or 1

Q = Last Q shifted left, fill LSBs with 1's.

Shift left

0

0

0

1

1

0 or 1

1

Q = Last Q shifted right, fill MSBs with 1's.

Shift Right

0 or 1

1

0

0 or 1

0 or 1

0 or 1

0 or 1

Synchronous Set To value

Synchronous set

0 or 1

0

1

0 or 1

0 or 1

0 or 1

0 or 1

Synchronous Reset To value

Synchronous reset

0 or 1

1

1

0

0

0 or 1

0 or 1

0 or 1

Last Q

Illegal concurrent SET and RST

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_054_shiftregmbitsoas_example.zip.

To simulate this design, follow these steps:

  1. Unzip the archive to a location on your computer.
  2. To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

This example of the multi-bit shift register uses two Digital Signal Sources to generate the input pulses to the multi-bit shift register. The input source waveforms are defined in a text file with each state transition defined on a single line. These two sources excite every state transition in the truth table.

For clarity, the simulation waveforms taken from the circuit example have been divided into two sections.

Load and Multi-bit Shift operations: 0-1us

The image below shows the load and shift behavior of the multi-bit shift register. The initial condition of the multi-bit shift register (is set to 255 decimal in the example.

Load and Multi-bit Shift
Time Event Q Output (binary)

100n

Load

0000 0101

200n

Retain state

0000 0101

300n

Shift left 4 places

0101 0000

400n

Shift right 2 places

0001 0100

500n

Shift right 2 places

0000 0101

600n

Shift left 2 places, fill with 1's

0001 0111

700n

Shift right 2 places, fill with 1's

1100 0101

900n

Load

0000 0101

Asynchronous and Synchronous Set/Reset: 1-2us

The image below shows the set/reset behavior of the Register.

Asynchronous Set/Reset
Time Event Q Output

1.3u

Load

5

1.52u

Asynchronous set

200

1.62u

Asynchronous reset

1

1.7u

Load

5

1.82u

Illegal concurrent ASET and ARST

5

Subcircuit Parameters

Because the multi-bit shift register model is generated by a template script when the simulation is executed, a fixed model cannot be inserted into a netlist. The template script for this device is simplis_make_register_model.sxscr, which you, as a licensed user, can download in a zip archive of all built-in scripts.

To download this zip file, follow these steps:

Note: You will be prompted to log in with the user name and password given to you when you registered.

  1. Click here to go to the product-installation page on the SIMetrix website.
  2. Click Download Links in the first paragraph of the product-installation web page.
  3. Scroll down to the Built-in Scripts section.
  4. Right click on Download and select Save target as..., and then navigate to a location on your computer to save the zip file.