In the previous section, Generating Efficiency Plots with Multi-Step Runs in DVM, you learned how to measure and plot the efficiency of the LLC converter over the line and load range. This is a classic verification example where the converter has already been designed and the testplan verifies the "goodness" of the design.
In this topic you will learn how to use DVM during the design process, that is, to optimize a particular design parameter using DVM. This kind of simulation is more akin to a Design of Experiments than a final verification. In this design of experiments, you will see how DVM can be used to analyze the deadtime for a synchronous buck converter.
To download the examples for the Applications Module, click Applications_Examples.zip
In this topic:
In this topic, you will learn the following:
To get started, open the schematic apps_d_2_buck_converter.sxsch. This schematic has been prepared to run DVM as described in the DVM Principles topic. The compensator design was taken directly from the SIMPLIS Tutorial, and a complete parameterized driver model has been added.
The LLC converter used in the last example has an input voltage of 380V, and an output voltage of 24 volts at 120W. The synchronous buck converter design you just opened has a 12V input and 1.2V output at 12W. In this exercise you will see how easy it is to modify the LLC efficiency testplan to run on the synchronous buck converter. When modifying an existing testplan for a new schematic there are three areas to look out for:
Next, you will modify the testplan in Excel.
To get started, open the syncbuck_efficiency.testplan in a spreadsheet program. For reference, the testplan is shown below:
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*** apps_d_1_efficiency_multi_step.testplan | ||||||||
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*?@ Label | Objective | Analysis | Analysis | Change( V1.DC_VOLTAGE , 380 ) | Change( I1.LOAD_RESISTANCE , 5 ) | Create | Create | Postprocess |
*** | ||||||||
Efficiency|Step VIN and ILOAD | Steady-State | Multi-Step( ILOAD , LIN , 10 , 0.5 , 5.0 ) | Multi-Step( VIN , LIST , 360 , 380 , 400 ) | {VIN} | {RLOAD} | Alias( Efficiency , Efficiency_WHEN_VIN_%VIN% ) | Alias( Efficiency , Efficiency_WHEN_ILOAD_%ILOAD% ) | |
Efficiency|Generate Efficiency Curves | NoSimulation | ./scripts/apps_d_1_create_xy_plots.sxscr |
Notice there are hard-coded reference designators V1 and I1 as well as hard-coded input voltage and output load current values in the Analysis columns. The hard-coded reference designators are not an issue in this case - the two schematics happen to have the same reference designators for the source and load. Also the postprocess script has the input voltage values hard-coded in it. In this example you will modify each value in turn.
Your final testplan should look like the following, with changed elements in red text:
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*** syncbuck_efficiency.testplan | ||||||||
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*?@ Label | Objective | Analysis | Analysis | Change( V1.DC_VOLTAGE , {VIN} ) | Change( I1.LOAD_RESISTANCE , {RLOAD} ) | Create | Postprocess | |
*** | ||||||||
Efficiency|Step VIN and ILOAD | Steady-State | Multi-Step( ILOAD , LIN , 10 , 0.5 , 9.5 , num_cores=4 ) | Multi-Step( VIN , LIST , 10.8 , 12 , 13.2 ) | {VIN} | {RLOAD} | Alias( Efficiency , Efficiency_WHEN_VIN_%VIN% ) | ||
Efficiency|Generate Efficiency Curves | NoSimulation | ./scripts/apps_d_2_create_xy_plots.sxscr |
Now you are ready to run this testplan on the schematic. To run the testplan,
After the testplan executes you should see the efficiency curves for the converter, similar to:
Before moving onto modifying the testplan to step the deadtime, a comment should be made on the number of data points used in these simulations. In the training course environment, users will have laptops with all sorts of processors and limitations - some computers will be very fast, others slow. For the purposes of demonstration during the class, we have chosen examples which simulate quickly. You should easily be able to modify these testplans to produce higher fidelity images, such as this one in which the ILOAD parameter was stepped from 0.5A to 5A in a decade sweep using 100 points per decade. The almost resonant effect seen in the low current efficiency is due to the discontinuous nature of the converter at light loads.
Now that you have successfully modified the testplan to generate the efficiency curves for this converter, you will make a few more changes to the testplan to:
You can start with the testplan which you completed in the last section; however, it might be better to start with the pre-prepared apps_d_2_efficiency_multi_step.testplan file. This file should be identical to the one you modified and saved as syncbuck_efficiency.testplan. To avoid the complications of Excel mangling the filename, you will start by making a copy of the apps_d_2_efficiency_multi_step.testplan file in Windows Explorer. To get started, you will need to make a copy of the testplan
Next, you will modify the testplan in Excel.
Now you are ready to run this testplan on the schematic. To run the testplan,
After the testplan executes you should see the efficiency curves for the converter, with the deadtime as the running parameter. Your curves should be similar to:
You can also "slice" the above data vertically by stepping the deadtime on the horizonal axis while the load current is the running parameter. In the graph below, the deadtime is stepped from 1ns to 30ns while the load current is stepped from 0.5 to 9.5A. The apps_d_4_efficiency_multi_step_step_deadtime_v_iload.testplan testplan was used to generate these curves.