SystemDesigner Buses

SystemDesigneruses a unique bus system to encode and transfer SystemDesignerspecific data from one SystemDesigner component to another. Although these buses have the same graphical look as other buses on a schematic, they need to be treated differently for probing and connecting to other devices. You first need to determine if the bus is a SystemDesignerbus.

As a rule, a bus is a SystemDesignerbus if one or both of the following are true:

• A bus connects the output of one SystemDesignercomponent to the input of another SystemDesignercomponent. For example, this condition exists in the tutorial example at the interconnection between the output of the ADC and the two probes as illustrated below.
• The other condition that determines a SystemDesigner bus is if the bus is connected to the output of a SystemDesignercomponent that drives another SystemDesigner component.

  For example in the global start of conversion ( SOC ) example, a SystemDesigner component drives the input to an ePWM as shown below:

  • The bus connected between the right-shift output and the ePWM-CMPA input pin is a SystemDesignerbus.
  • The other bus in the this schematic is also a SystemDesigner bus connected to the output of a SystemDesigner adder block.

A bus is not a SystemDesignerbus if one of the following condition exists:

• The output bus pin on a device has the [0..n] label where n is a positive integer, such as the debug pins on the ePWM symbols, shown below from the global start of conversion ( SOC ) example. In this schematic, the tbctr probe is on a regular bus, not on a SystemDesigner bus.