SystemDesigner Limiter

The SystemDesigner Limiter limits the maximum and minimum amplitudes of a SystemDesigner bus. The maximum and minimum amplitudes can be any integer value. The Limiter output is a SystemDesigner bus with a 32-bit signed-integer or floating-point result.

The propagation delay can be defined as a fixed time, as asynchronous to any clock, or as a synchronous delay where the delay is a number of SystemDesigner -clocks cycles. In this release of SystemDesigner , the synchronous delay is supported only for integer-sampled data simulations.

In this topic:

Model Name:

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector Menu Location:

SystemDesigner Functions (max. 32 bit)

Symbol Library:

SIMPLIS_SystemDesigner.sxslb

Model Library:

SIMPLIS_SystemDesigner.lb

Subcircuit Name:

SIMPLIS_SD_LIMITER_32 : limiter

Symbol:

limiter

Multiple Selections:

Only one device at a time can be edited.

Editing the SystemDesigner Limiter

To configure the SystemDesigner Limiter, follow these steps:

Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
Make the appropriate changes to the fields described in the table below the image.

Label	Parameter Description
Use asynchronous delay	Implements a combinatorial model where the output voltage changes in response to the input voltage change after a propagation delay.
Propagation delay	The propagation delay from an input change to an output change in seconds. This parameter is used only in models with Asynchronous delay.
Use synchronous delay	In response to an input voltage change, the output voltage changes after a designated number of clock cycles.
Delay	The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge . This parameter is used only in models with Synchronous delay.
Clock source	Specifies the global clock used for the Limiter. The Clock can be set up using the SystemDesigner->Edit SystemDesigner Clocks... menu item or by placing a Start of Conversion Breakin.
Trigger edge	Sets the Limiter output to change on specific edges of the Clock: 0_TO_1 The output changes only on rising edges of the Clock source 1_TO_0 The output changes only on falling edges of the Clock source
Use asynchronous delay	Implements a combinatorial model where the output voltage changes in response to the input voltage change after a propagation delay.
Propagation delay	The propagation delay from an input change to an output change in seconds. This parameter is used only in models with Asynchronous delay.
Use synchronous delay	In response to an input voltage change, the output voltage changes after a designated number of clock cycles.
Delay	The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge . This parameter is used only in models with Synchronous delay.
Clock source	Specifies the global clock used for the Limiter. The Clock can be set up using the SystemDesigner->Edit SystemDesigner Clocks... menu item or by placing a Start of Conversion Breakin.
Trigger edge	Sets the Limiter output to change on specific edges of the Clock: 0_TO_1 The output changes only on rising edges of the Clock source 1_TO_0 The output changes only on falling edges of the Clock source

Examples

The Limiter circuit example can be downloaded here: simplis_115_systemdesigner_limiter_example.sxsch. In order to simulate this design, follow these steps:

If you currently have a dialog box open in SIMetrix/SIMPLIS, cancel that dialog box so that the example can open in SIMetrix/SIMPLIS.
Unzip the archive to a location on your computer.
To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

The circuit example below uses an ADC to generate the input to the Limiter LIMITER_1. The Limiter is set with the maximum limit of 5 and the minimum limit of -2. The output is limited to values between these limit values for all simulations.

During floating-point simulations, the Limiter also limits the input signal, producing a limited double-precision floating-point output.

The AC transfer function for the Limiter is shown below. As expected, the gain is 0dB with no phase change.