SIMPLIS Simulation Options

Save options

• All: If selected, all voltages and currents at the top level will be saved. To save voltages or currents inside a hierarchy, you must use the .KEEP statement.
• Voltages only: If selected, only top level node voltages will be saved
• Probes only: If selected only voltages and currents that are explicitly probed will be output. This applies to all levels of the circuit hierarchy.

No Forced Output Data

Normally, SIMPLIS will add a point before and after a logic device changes state. These extra point ensure the graph waveform will display a logic edge. Checking this box will inhibit the extra points which define logic gate output transitions.

Force New Analysis

This tells SIMPLIS to ignore any state information that it may have stored and which could be used to speed up the run. For example, any stored snapshots (see SIMPLIS Transient Analysis) will not be used if this is selected.

To learn more about placing .KEEP statements in a schematic hierarchy, see the Advanced SIMPLIS Training topic: .KEEP Statement in the Hierarchy.