SystemDesigner Unit Delay

The SystemDesigner Unit Delay models a unit delay in the z-domain. The model used by the Unit Delay is identical to the Data Register; only the symbol is different. The Unit Delay can be clocked with any SystemDesigner clock. From the Output parameter box, you can limit the resulting output to either signed or unsigned numbers with fewer than 32 bits.

The propagation delay can be defined as a fixed time, as asynchronous to any clock, or as a synchronous delay where the delay is a number of SystemDesigner -clocks cycles. In this release of SystemDesigner , the synchronous delay is supported only for integer-sampled data simulations.

In this topic:

Model Name:

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector Menu Location:

SystemDesigner Functions (max. 32 bit)

Symbol Library:

SIMPLIS_SystemDesigner.sxslb

Model Library:

SIMPLIS_SystemDesigner.lb

Subcircuit Name:

SIMPLIS_SD_UNIT_DELAY_32 : unit delay

Symbol:

unit delay

Multiple Selections:

Only one device at a time can be edited.

Editing the SystemDesigner Unit Delay

To configure the SystemDesigner Unit Delay, follow these steps:

Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
Make the appropriate changes to the fields described in the table below the image.

Label	Parameter Description
Clock source	Specifies the global clock used for the Unit Delay. The Clock can be set up using the SystemDesigner->Edit SystemDesigner Clocks... menu item or by placing a Start of Conversion Breakin.
Trigger edge	Sets the Unit Delay output to change on specific edges of the Clock: 0_TO_1 The output changes only on rising edges of the Clock source 1_TO_0 The output changes only on falling edges of the Clock source
Use asynchronous delay	Implements a combinatorial model where the output voltage changes in response to the input voltage change after a propagation delay.
Propagation delay	The propagation delay from an input change to an output change in seconds. This parameter is used only in models with Asynchronous delay.
Use synchronous delay	In response to an input voltage change, the output voltage changes after a designated number of clock cycles.
Delay	The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge . This parameter is used only in models with Synchronous delay.
Clock source	Specifies the global clock used for the Synchronous delay block. The Clock source can be set using the SystemDesigner->Edit SystemDesigner Clocks... menu item or by placing a Start of Conversion Breakin.
Trigger edge	Sets the output to change on specific edges of the Clock source: 0_TO_1 The output changes only on rising edges of the Clock source 1_TO_0 The output changes only on falling edges of the Clock source This parameter is used only in models with Synchronous delay.
Use asynchronous delay	Implements a combinatorial model where the output voltage changes in response to the input voltage change after a propagation delay.
Propagation delay	The propagation delay from an input change to an output change in seconds. This parameter is used only in models with Asynchronous delay.
Use synchronous delay	In response to an input voltage change, the output voltage changes after a designated number of clock cycles.
Delay	The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge . This parameter is used only in models with Synchronous delay.
Clock source	Specifies the global clock used for the Synchronous delay block. The Clock source can be set using the SystemDesigner->Edit SystemDesigner Clocks... menu item or by placing a Start of Conversion Breakin.
Trigger edge	Sets the output to change on specific edges of the Clock source: 0_TO_1 The output changes only on rising edges of the Clock source 1_TO_0 The output changes only on falling edges of the Clock source This parameter is used only in models with Synchronous delay.

Examples

A circuit example using the SystemDesigner unit delay can be downloaded here : simplis_125_systemdesigner_unit_delay_example.sxsch. In order to simulate this design, follow these steps:

If you currently have a dialog box open in SIMetrix/SIMPLIS, cancel that dialog box so that the example can open in SIMetrix/SIMPLIS.
Unzip the archive to a location on your computer.
To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

In this example, a complete integrator is implemented using the Unit Delay, U_DELAY_1, to store the previous error sample. The function then does the following in this order:

The integrator uses the trapezoidal rule integration method to integrate the incoming error signal.
Another unit dela,y U_DELAY_2, accumulates the result of previous samples.
The adder then adds the two analog signals and produces the output: Sum = Error N0 + Error N1.
The Sum is then gained by the GAIN_1 block and divided by 2 using the shift right operation SHIFT_1.
Finally, the accumulator implemented with U_DELAY_2 and ADDER_3 stores the accumulated results.

Note the quantization of the integrator output in the integer-type simulations:

In the floating-point simulation, there is no quantization of the integrated signal.

The AC transfer function for the integrator is shown below.