SIMetrix Extensions

In this topic:

In an Ideal World...

While that is our idealistic intention, reality never allows ideals. Verilog-A has quite a few little limitations that we would not want to impose on our users. Some of these we have already addressed and made non-standard extensions to do so. These are detailed below.

We will endeavour in the long run to make such extensions in a manner that would allow a source file to work with other Verilog-A simulators without modification.

Instance Parameters

The Verilog-A language does not distinguish between instance parameters and model parameters. An instance parameter is one that can be defined on the device line on a per instance basis whereas a model parameter is one defined in a .MODEL statement. The most flexible implementation is one that allows both, with the instance parameter taking precedence if both are specified by the user. However this method has a cost in terms of increased memory usage per instance. While memory consumption may not seem to be a big issue, it can impact on performance. The less memory used, the more likely that the processor will find what it wants in the cache. For this reason it is desirable to minimise the number of instance parameters.

The SIMetrix Verilog-A implementation provides two methods of defining instance parameters: one in the verilog-A source file and the other on the command line of va.exe which in turn can be passed from .LOAD.

To define an instance parameter in the .VA file, prefix the parameter key word with the special attribute 'type' with a value of "instance". This is how it should look:

(* type="instance" *) parameter a = 1 ;

To define on .LOAD, add the parameter "instparams=parameter_list" where parameter_list is a comma separated list of parameter names.

If a parameter is defined as an instance parameter, it will also be available as a model parameter. If both are specified, the instance value will take precedence.

SPICE compatibility

Verilog-A defines a number of features that allow interfacing between the SPICE simulator and Verilog-A code. SIMetrix implements the ability to instantiate a SPICE device in a Verilog-A module as defined in the LRM 2.4, sections E.2.2.3 and E.3.

LRM 2.4 Features Supported

SIMetrix Verilog-A supports all primitives as described in Table E.1 of LRM 2.4 with the following exceptions and differences

  • vsine, isine: parameters supported: dc, mag, phase, offset, ampl, freq, td, sinephase. Other parameters not supported. Additionally supports theta parameter which implements an exponential decay
  • diode, bjt, mosfet and jfet implement level 1 devices by default. Add a LEVEL parameter to specify other models.

Additional SPICE Devices

The SIMetrix device internal device name may be used to specify any device type. For a list of available internal names run the built-in script show_devices from the SIMetrix command line. This will copy to the clipboard a complete list. The name in the first column may be used provided your license supports it. Note that digital devices may not be used.

Output Variables

Output variables are values that can be plotted and are also listed in the .out file if ".op" or ".options opinfo" is specified in the netlist. Further, they can be accessed using the $simprobe function.

Normal real-valued variables may be defined as output variables by prefixing the definition with a special attribute. The full form is:

(* desc="description", units="units")real varname ;
Where units is one of:
  • "V"
  • "A"
  • "Secs"
  • "Hertz",
  • "Ohm",
  • "Sie",
  • "F",
  • "H",
  • "J",
  • "W",
  • "C",
  • "Vs",
  • "V^2",
  • "V^2/Hz",
  • "V/rtHz",
  • "A^2",
  • "A^2/Hz",
  • "A/rtHz",
  • "V/s",
  • "Celsius"
  • "coul"
  • ""

description is an arbitrary description of the variable. Note that description is currently unused.

If either description or units is present, the variable will be marked as an output variable.

To plot an output variable, add a .GRAPH statement to the netlist (or F11 window) in the form:

.GRAPH instance_ref#variable_name

Alternatively to instruct SIMetrix to save the data for the output variable without immediately plotting it, use ".KEEP" instead of ".GRAPH".

Device Mapping

You may control how the new device is represented in SIMetrix using a device mapping. This does the same as the sxcfg file. Mappings are applied as a module attribute in the form:

( * Mappings="mapping_defs" * )

This should prefix the "module" keyword.

mapping_def is a semi-colon delimited list of mapping definitions. Each mapping definition is itself a comma delimited list of attibutes in the following order:

model-type-name,level-number,device-letter,default-parameter,version

Where:
model-type-name The name used in the .MODEL statement.
level The LEVEL parameter value in the .MODEL statement.
device-letter The device letter to use for this device.
default-parameter A single parameter name and value. This is intended to be used to define device polarity. E.g. "pnp=1" might define a PNP BJT. This is useful to allow the definition of BJTs and MOS devices using conventional NPN/PNP or NMOS/PMOS model type names.
version Value of VERSION parameter.

For example, the HICUM device is defined with the following mapping:

(* Mappings="hicum_211,0;npn,8,Q,pnp=0,;pnp,8,Q,pnp=1," *)

This has three mappings. You can use hicum_211 with no level parameter to define a model. In this case the pnp parameter would need to be set for a PNP device. Alternatively you can use NPN as a model type name along with LEVEL=8 for an NPN device, or PNP with LEVEL=8 for a PNP device.

Tolerances

The Verilog-A language only allows for absolute tolerances to be hardwired in the VA source file. This means for example, that absolute current tolerance, must be specified as a fixed constant which cannot be changed in the .OPTIONS line or anywhere else.

SIMetrix provides a workaround for this using the special values $abstol, $vntol, $chgtol and $fluxtol. These can be used to define absolute tolerances in electrical nature definitions. These are already used in the standard discipline header files supplied with the SIMetrix Verilog-A compiler.

Analysis() Function

Additional analyis types:

  • "sens" sensitivity analysis
  • "tf" transfer function analysis
  • "pta" pseudo-transient analysis
  • "smallsig" small signal analysis
  • "rtn" real time noise analysis

$simparam() Function

Standard types supported by SIMetrix:

  • "gdev"
  • "gmin"
  • "simulatorSubversion"
  • "simulatorVersion"
  • "sourceScaleFactor" - includes pseudo transient scale factor
  • "tnom"

Additional SIMetrix extensions:

"ptaScaleFactor" - as "sourceScaleFactor" but functional in pseudo transient analysis only. Default = 1.0.

In addition you can specify any option setting defined using .OPTIONS. E.g. $simparam("reltol") will return the value of the RELTOL option.

$fopen() Function

Use the argument "<listfile>" to write to the list file. This is the file created by every simulation with the extension .OUT.