SIMetrix Verilog-A vs LRM 2.4

In the following we have highlighted areas where the SIMetrix Verilog-A compiler is not compliant with the LRM 2.4 standard.

In this topic:

2.6 Numbers

All number formats are accepted except sized values, e.g. 4'h1234. Also the signed prefix (s or S) is not recognised.

The LRM allows for the base prefix (e.g. 'b or 'h) and the value to be individually macro substituted. This is not currently supported. The number as a whole may be macro substituted but not individual components.

Hex, binary and octal values are allowed. E.g. 'hFF is 255 as is 'b11111111 and 'o377. All hex, binary and octal values are unsigned that is the leading bit in such a number is never interpreted as a sign bit. However a unary '-' may prefix any value.

All integer values are represented as signed 32 bit values. This means that the largest unsigned value that can be represented is ???MATH???2^{31}???MATH???-1. Any larger value entered will be interpreted as ???MATH???2^{31}???MATH???-1; no error message will be displayed.

2.7 String Literals

String literals are not supported but the string data type is supported. See LRM 2.4, 3.3

2.8 Identifiers, Keywords, and System Names

The LRM requires that all identifiers are case sensitive. SIMetrix Verilog-A complies with this except that parameters and instance names cannot be distinguished exclusively by case. For example, this would lead to an error:

parameter real BANDWIDTH = 300.0 ;
parameter real bandwidth = 500.0 ;

The above is legal Verilog-A but the simulator's parameter handling is not case-sensitive so it would not be possible to distinguish between the above two parameters. However, case-sensitivity is maintained within the Verilog-A module. The following would be allowed:

parameter real BANDWIDTH = 300.0 ;
real bandwidth ;

Note also that localparam objects that differ only by case are permitted.

The same rules also apply to instance names used for hierarchical structures.

2.9 Attributes

Attributes are supported for variables, parameters and module declarations.

3.4.2 Parameters - Value Range Specification

Fully compliant. Note that an apostrophe is required before a string value range specification. This changed from LRM 2.2 and some older Verilog-A designs will show a syntax error if the apostrophe is omitted.

3.4.3 Parameter Units and Descriptions

Syntax for "desc" and "units" is recognised but non-functional.

Non-standard SIMetrix attribute "instance" has been implemented. This defines the parameter as an instance parameter, that is, its value can be set on the device line. See Instance Parameters.

3.6.2.2 Domain Binding

Anything other than "domain continuous" will raise an error.

3.6.2.3 Natureless Disciplines and Domainless Disciplines

Accepted but non-functional

3.6.2.4 Disciplines of Nets and Undeclared Nets

Not supported

3.6.2.7 User Defined Attributes

Accepted but non-functional

3.6.3.1 Net Descriptions

Not implemented. This will lead to a syntax error if used.

3.6.3.2 Net Discipline Initial (Nodeset) Values

Not implemented. This will lead to a syntax error if used.

3.6.5 Implicit Nets

Not meaningful as hierarchical structures are not yet implemented.

3.7 Real Net Declarations

Not supported in Verilog-A

3.8 Default Discipline

Not supported in Verilog-A

3.9 Disciplines of primitives

Not supported in Verilog-A

3.10 Discipline Precedence

Discipline of all nets is defined in the local module only. Out-of-module references are not implemented.

3.11 Net compatibility

This is partially implemented within the simulator. If you connect different disciplines together you will get a warning. But the inherited disciplines will not be compatible, only the same disciplines may be inter-connected. ... and you only get a warning not an error.

3.12 Branches

Compliant for scalars only. Currently named vector branches are not supported. Unnamed branches are however fully supported.

Discipline compatibility is checked, but it seems that the discipline for each node in a branch must be identical. The spec requires them to be 'compatible' which is not the same thing.

Minor issue: if a branch is unused then the discipline of each node will not be checked at all and no error will be raised if they are incompatible. This is not defined in the standard.

4.2.6 Case Equality Operator

Not supported in Verilog-A

4.2.13 Concatenations

String concatenations are supported, Numeric concatenation are unsupported.

4.2.14 Assignment Patterns

Simple assignment patterns are supported. Replication multiplier is not supported.

4.3 Built-in Mathematical Functions

All functions supported. Verilog-HDL style functions with '$' prefix are now supported.

4.5.15 Restrictions on Analog Operators

SIMetrix Verilog-A is mostly compliant with this section with the exception detailed below.

Analog operators (such as ddt, transition etc) are not allowed in places where their execution could be dependent on values that change during the course of a simulation. This is because analog operators store state information which could become invalid. SIMetrix does not always implement this restriction correctly and there are situation where it will allow you to use an analog operator but shouldn't.

4.5.3 Time derivative Operator

Compliant except tolerance is currently ignored.

4.5.4 Time integral operator

Fully implemented except abstol and nature parameters. These parameters are accepted but are non-functional.

4.5.5 Circular Integral Operators

Fully implemented except abstol and nature parameters. These parameters are accepted but are non-functional.

4.6.1 Analysis

Compliant except for "nodeset"

4.6.2 DC analysis

Compliant except for "nodeset"

4.6.4.3 noise_table

Not implemented

4.6.4.4 noise_table_log

Not implemented

4.7.1 Defining an Analog Function

Compliant except cannot use local parameters

4.7.2 Returning a Value from an Analog Function

Partially compliant. Can use return value for output. Output via passed argument is not supported.

5.10.3.4 absdelta Function

Not relevant for Verilog-A

6 Hierarchical Structures

Hierarchical structures are currently partially supported. It is possible to instantiate Verilog-A modules provided they satisfy the following:
  1. Connections are ordered only. Named connections are not supported
  2. Parameters are named only. Ordered parameters are not supported
  3. Nodes are scalar. Vectors are not supported
  4. generate blocks are not used

7 Mixed Signal

Not implemented in Verilog-A

8 Scheduling Semantics

Most of this section is concerned with Verilog-AMS which is the mixed-signal version and so is not relevant.

9.6 Timescale system tasks

Not relevant for Verilog-A

9.7.1 $finish System Task

$finish compliant except behaviour of function argument differs from LRM. See $finish

9.7.2 $stop System Task

$stop compliant except argument to function is ignored. $stop will cause the simulation to pause in the same way as clicking on the Pause button in the simulator status box. To resume after a call to $stop, click on the Resume button in the simulator status box or the equivalent menu.

9.8

Not relevant for Verilog-A

9.9

Not relevant for Verilog-A

9.10 Simulator time system functions

$abstime compliant. $realtime not supported and now deprecated

9.11

Not relevant for Verilog-A

9.12

Not relevant for Verilog-A

9.13.1 $random and $arandom Functions

Compliant except SIMetrix is lenient on usage of type_string. LRM 2.4 states that the type_string argument is only accepted for paramset statements used to assign parameter values. SIMetrix allows type_string to be used anywhere although a warning condition will be raised if used in an analog block.

9.13.2 Distribution Functions

All functions implemented. See notes on $arandom with regard to type_string parameter.

9.15 Analog kernel parameter system functions

$temperature, $vt, $simparam and $simparam$str compliant.

9.17.1 $discontinuity

Reports a discontinuity in the main equation if argument is zero. Discontinuities reported in derivatives are ignored. Discontinuities should always be avoided and this function should never be used except as a temporary work around. It will not fix problems caused by discontinuities but will enable some strategies that overcome some of the problems that they cause at the expense of simulation accuracy.

9.17.3 $limit

Compliant using built-in "pnjlim". User functions not implemented.

9.18 Hierarchical System Parameter Functions

$mfactor implemented. Others are not

9.19 Explicit binding detection system functions

Both $param_given and $port_connected are compliant

9.20 Analog node alias system functions

Not implemented

9.22

Not relevant for Verilog-A

9.23

Not relevant for Verilog-A

10 Compiler directives

These directives are compliant:

'define, 'else, 'endif, 'ifdef, 'include, 'undef

Predefined macros are not implemented

11, 12

Not implemented

Annex E

SIMetrix Verilog-A supports access to SPICE primitives as described in E.2.2.3. See SPICE compatibility