SIMPLIS IGBT Models

Any SPICE IGBT model installed in the SIMetrix library can be converted for use in SIMPLIS. When a IGBT is placed on a SIMPLIS schematic, a model parameter extraction routine is invoked to automatically convert the SPICE model to a SIMPLIS model. During the model parameter extraction process, SIMetrix/SIMPLIS automatically runs several SPICE simulations on the SPICE model and extracts the SIMPLIS model parameters. After the Piecewise Linear (PWL) model parameters have been extracted, the resulting IGBT model will run in SIMPLIS.

In this topic:

Extracting the IGBT Parameters

When you place an IGBT symbol on a schematic, the Extract IGBT Parameters dialog opens for you to edit the default test conditions. You should change the test conditions to accurately reflect the expected voltage, current, and temperature of the device in your circuit.

The default test conditions are defined using the command shell menu, File > Options > SIMPLIS Options... . For additional information, see SIMPLIS IGBT Options.

The following table describes the Extract IGBT Parameters dialog test conditions.

Extracted IGBT Model

Test Condition Default Value Units Description
SPICE Model IRF530   The SPICE model used to extract SIMPLIS parameters.
Model type Extracted   Invokes the model parameter extraction algorithms.
Collector to emitter voltage 2k V The peak off-state voltage seen by this device.
Used to extract capacitance for model levels which include parasitic capacitance.
Breakdown is not modeled.
Gate drive voltage 15 V Gate to emitter voltage to extract RDS(on).
Collector current 200 A Peak collector current to extract the RDS(on) and forward gain of the IGBT.
Model temperature 25 °C Temperature used for all extraction simulations.
Model level 0   Model complexity. For information on choosing the model level, see IGBT Model Levels.
Limit maximum off resistance Checked none Limits the off resistance for the IGBT. For some SPICE models, this will produce a SIMPLIS model which runs faster.
Maximum off resistance 100Meg The maximum off resistance of the IGBT switch. This value is used only if "Limit maximum off resistance" is checked.

Show extracted PWL waveforms option

Beginning in version 8.2, there is now an option to plot the extracted parameters as a set of PWL curves. To enable this option, select the Show extracted PWL waveforms checkbox and extract the model. After the model is extracted, a set of curves will be generated comparing the extracted PWL curves against the simulated SPICE curves. The curves displayed will depend on the model level being extracted.

Below is a typical PWL approximation of the charge vs. voltage characteristic of the Collector-Emitter capacitor. As SIMPLIS uses the charge vs. voltage in a simulation, this characteristic curve is used to curve fit the non-linear capacitance. As a result, the capacitance is piecewise constant, and is calculated from the charge vs. voltage characteristic. The SPICE curves are shown in red and the PWL curves in blue.

SIMPLIS IGBT Model Levels

The SIMPLIS IGBT models have multiple levels to balance simulation speed vs. model accuracy. There are currently four levels: 0, 1, 2, and 3. As the model level increases, so does the model complexity and, as a rule, simulation times also increase.

SIMPLIS extracts a model based on the model level chosen in the Extract IGBT Parameters dialog.

  • Currently model levels 0, 1, and 2 are supported by the model parameter extraction algorithms.
  • The level 3 model is intended for more detailed modeling and can be manually generated from a device datasheet or from a spreadsheet or other program. For details of the Level 3 model, see Manually Generate and Customize IGBT Models.
  • Although these models are internally saved as ASCII text, the following illustrations show the model levels in schematic form.

Level 0 Model

Level 0 models a switch with on/off resistance values, an anti-parallel diode, and gate capacitance. The Level 0 Model can be used  for AC Bode plots and for simulating output voltage during load and line transients when the actual switching waveform shapes are not critical.

  • The conduction region is modeled with an on and off resistance.
  • CGE capacitance is modeled with a linear capacitor and has a parallel 10Meg resistor.
  • Internal gate resistance is modeled with RG.
  • The anti-parallel diode is modeled with a 2- or 3-segment resistor; the number of segments is specified in the SIMPLIS Options dialog.
  • There is no output (CCE) or reverse capacitance (CCG).

Below is a schematic view of a Level 0 model:

Level 0 models these circuit elements Level 0 Schematic
QQ1: Switch with on and off resistance and saturation voltage
CGE: Linear capacitance
RGE: 10Meg Ω resistor
RG: Internal gate resistor
!R_AP_DIODE: Anti-parallel diode modeled by PWL resistor

Level 1 Model

Level 1 models a switch with on/off resistance values, anti-parallel diode, and gate capacitance, plus a lumped-linear Coss capacitance across collector and emitter terminals. The Level 1 Model can be used for power stage simulations, including Quasi-resonant, LLC, and phase-shifted bridge topologies,as well as for AC Bode Plots and for simulating output voltage during load and line transient.

  • The conduction region is modeled with an on and off resistance.
  • CGE capacitance is modeled with a linear capacitor and has a parallel 10Meg resistor.
  • Internal gate resistance is modeled with RG.
  • The anti-parallel diode is modeled with a 2- or 3-segment resistor; the number of segments is specified in the SIMPLIS Options dialog.
  • There is no reverse capacitance (CCG).
  • The bulk COSS capacitor is the parallel CCG and CCE capacitors with the value as follows:
    COSS = (QCCE1 - QCCE0)/(VCCE1 - VCCE0)

Below is a schematic view of a Level 1 model:

Level 1 models these circuit elements Level 1 Schematic
QQ1: Switch with on and off resistance and saturation voltage
CGE: Linear capacitance
RGE: 10Meg Ω resistor
RG: Internal gate resistor
!R_AP_DIODE: Anti-parallel diode modeled by PWL resistor
COSS: Lumped linear output capacitance

Level 2 Model

Level 2 models a switch with forward transconductance gain, a anti-parallel diode, and gate capacitance, plus a nonlinear Gate-Collector, Collector-Emitter, and Gate-Emitter capacitors. The active region is modeled by a linear transconductance gain (ICE is proportional to VGE - VT0). The Level 2 Model can be used for switching losses, IGBT voltage and current stresses, and all simulations covered by Level 0 and Level 1 models.

  • Forward conduction is modeled with a two-segment gain. The following gain information assumes that the device is being switched from an off state to an on state:
    • Below the threshold voltage (VT0 - HYSTWD/2), the gain is 0.
    • Above the threshold, the gain is GAIN = ICE2/(VGE2 - VT0 - HYSTWD/2) units: A/V (transconductance)
  • Internal gate resistance is modeled with RG.
  • The anti-parallel diode is modeled with a 2- or 3-segment resistor; the number of segments is specified in the SIMPLIS Options dialog.
  • This model level implements non-linear capacitors for all three capacitors (CGE , CCG and CCE). The Model Extraction algorithms determine the number of segments for each capacitor. Typically the Gate-Emitter capacitor is linear, while the Collector-Gate and Collector-Emitter capacitors have four segments.
    Note: The actual capacitor used is determined by the CGE_NSEG , CDE_NSEG and CDE_NSEG parameters.
    • If one of these parameters is set to 0, the capacitor at that  location will be an open circuit.
    • If the number of segments is set to 1, a linear capacitor is implemented with capacitance: Cxx = (Qxx1 - Qxx0)/(Vxx1 - Vxx0)

      where "xx" is the capacitor GE, CG, or CE.

    • Otherwise, if the CXX_NSEG parameter is set to a value greater than 1, the capacitor is implemented with a PWL capacitor. For more information, see See Capacitance Models section below.                          

Below is a schematic view of Level 2 model:

Level 2 models these circuit elements: Level 2 Schematic
QQ1: Switch with forward transconductance, on and off resistance and saturation voltage
RG: Internal gate resistor
CGE: PWL capacitance
RGE: 10Meg Ω resistor
CCG: PWL capacitance
CCE: PWL capacitance
!R_AP_DIODE: Anti-parallel diode modeled by PWL resistor

Level 3 Model

The Level 3 model extends the Level 2 model to include up to 5 forward transconductance gain segments. The Level 3 model can be used to more accurately model converter losses, and converters which operate over a wide range of currents.

Note: The model extraction algorithms do not extract a level 3 model. The level 3 model is available for manually generated models. See Customize or Manually Generate IGBT Models for details.
  • The level 3 model is the same as the Level 2 model but the Forward Conduction is modeled with a variable number of PWL segments.
  • As with the Level 2 model, the first segment has a gain of 0.
  • The second segment has a gain of GAIN2 = ICE2/(VGE2 - VT0)  units: A/V (transconductance)
  • Further segments have gain values which are defined by the slopes between successive point pairs.

    For example, the third segment has a gain of GAIN3 = (ICE3 - ICE2)/(VGE3 - VGE2) units: A/V (transconductance).

  • Up to five segments of gain can be used with this model. The number of gain segments is controlled by the GAIN_NSEG parameter.

Below is a schematic view of a Level 3 Model:

Level 3 models these circuit elements Level 3 Schematic
QQ1: Switch with forward transconductance, on and off resistance and saturation voltage
RG: Internal gate resistor
CGE: PWL capacitance
RGE: 10Meg Ω resistor
CCG: PWL capacitance
CCE: PWL capacitance
!R_AP_DIODE: Anti-parallel diode modeled by PWL resistor
!R_GAIN: PWL forward transconductance gain
G1: Converts gate-emitter voltage to a current

User-defined Models

The user-defined model uses parameters entered directly in the Edit IGBT Parameters dialog without invoking the model extraction algorithms. A IGBT can be switched from an extracted model to a user-defined model at any point; however the extracted parameters are by default copied over to the user-defined parameters, replacing any user-entered values. You can disable this behavior in the SIMPLIS Options dialog by clearing the check box labeled "Automatically copy extracted parameters to User-defined parameters." You can access these options from the command shell menu File > Options > SIMPLIS Options... . For more information, see SIMPLIS IGBT Options.

The following table describes the Edit IGBT Parameters entries.

User-defined IGBT Model

Parameters Default Value Units Description
Label: USER_LABEL    
Model type: User-defined    
On Resistance: 10m The on resistance of the IGBT switch.
Off Resistance: 100Meg The off resistance of the IGBT switch
Threshold: 2.5 V IGBT threshold voltage - the IGBT will turn on at (Threshold + 1/2 Hysteresis).
Turn off occurs at (Threshold  - 1/2 Hysteresis).
Hysteresis 250m V The Hysteresis of the IGBT
Input Capacitance 0 F The input capacitance ( CGE) of the IGBT. Set to 0 to remove the capacitor from the model.
Gate Resistance 0 The internal resistance of the IGBT. Set to 0 to remove the gate resistance from the model.
Output Capacitance: 0 F A non-zero value will place a linear capacitance between the IGBT collector and emitter terminals.
Set to 0 to remove capacitor from the model.
Anti-parallel diode Parameters
Forward voltage: 750m V Diode forward voltage drop. The diode effectively turns on at this voltage.
Forward resistance: 10m The Anti-parallel diode resistance at voltages higher than the Forward voltage.

User-defined Model Schematic

Models these circuit elements User-defined Schematic
QQ1: Switch with on and off resistance and saturation voltage
CGE: Linear input capacitance
RGE: 10Meg Ω resistor
RG: Internal gate resistor
!R_AP_DIODE: Anti-parallel diode modeled by PWL resistor
COSS: Lumped-linear output capacitance

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Customize or Manually Generate IGBT Models

You can customize or manually generate your own IGBT models using a parameter string with multiple PARAM_NAME=PARAM_VALUE key-value pairs. The parameter names and their functions are described in the IGBT Model Parameters section below. You can interpret the SIMPLIS parameter values from device datasheet specifications and curves.

You can compose the parameter string in a text editor, spreadsheet, or script. The order of the parameter names in the parameter string and the capitalization of the parameter names are irrelevant.

You can include a PROTECTED=1 key-value pair to prevent from extracting a model and overwriting your manually generated parameters. The PROTECTED=1 key-value pair is not used in the simulation.  

Note: When you click on the device after adding the PROTECTED=1 key-value pair, the following message box appears to warn you that this is a hand-edited model.

To customize or generate your own IGBT model, follow these steps:

  1. Create a parameter string of multiple PARAM_NAME=PARAM_VALUE key-value pairs using your preferred text editor, spreadsheet or script.
  2. Add the PROTECTED=1 key-value pair to the parameter string.
  3. Extract a IGBT model and place it on a schematic.
  4. Right click on the symbol and select Edit/Add Properties....
  5. Double click on the PARAM_VALUES property.
    Result: The Edit Property dialog opens.
    At this point, you can change individual parameters in the Value box, or replace the entire default properties with the parameter string that you created in Step 2.
  6. To replace the entire string, follow these steps:
    1. Click in the Value box and type Ctrl A to select all of the existing parameter string, and press Delete.
    2. Copy the parameter string you completed in Step 2 and paste into the Value box.
    3. Click Ok.
  7. To change the name of your customized model, double click the VALUE property in the Edit Properties dialog, and change the name in the Value box.
  8. To return to the schematic, click Ok.
Alternately you can write the PARAM_VALUES property to the symbol using the Prop command in the command line with the following syntax:  
prop PARAM_VALUES parameter_string
where parameter_string is the set of key-value pairs that you created in Steps 1 and 2 above.
Important: Since parameter_string contains spaces, the entire string must be enclosed in double quotes.

IGBT Model Parameters

The following tables detail the parameters which define the electrical behavior of the IGBT model. Several other parameters in the PARAM_VALUES property have no effect on the electrical behavior of the model. These parameters are used to populate the Extract IGBT Parameters dialog box.

Note: The default values are unlikely to appear in an extracted model. If these parameter values appear in your design, there has been an error in composing the parameter string.

IGBT Parameters

Parameter Name Default Value Description
LEVEL 0 Model Level
RCEON 10m Switch QQ1 On resistance
ROFF 100Meg Switch QQ1 Off Resistance
VCE_SAT 1 Switch QQ1 Saturation Voltage
VT0 2.5 Switch QQ1 Threshold
HYSTWD 1 Switch QQ1 Hysteresis
RG 1.123456789 Gate Resistance

Gain Model Parameters (LEVEL = 2 and 3 only)

Parameter Names Default Value Description
GAIN_NSEG   2 (off and on) Number of segments in the Gain model
VT0   1.123456789 X-Y point definitions for gain:
  • X-axis is gate-emitter voltage in volts (V).
  • Y-axis is collector current in amps (A).
  • The model adds zeros for VGE0, ICE0, and ICE1.
  • Points with subscripts greater than the GAIN_NSEG parameter are ignored.
The parameters listed in green are used only in Level=3 models.
VGE2 ICE2 1.123456789
VGE3 ICE3 1.123456789
VGE4 ICE4 1.123456789
VGE5 ICE5 1.123456789

Anti-parallel diode Model Parameters

Parameter Names Default Value Description
BD_NSEG   3 Number of segments in the anti-parallel diode model.
  • BD_NSEG=0 removes diode.
  • Valid BD_NSEG are 0 , 2 , 3, 4, 5, 6
VD0 IBD0 1.123456789 X-Y point definitions for anti-parallel diode:
  • X-axis is the Emitter-Collector voltage in volts (V).
  • Y-axis is the Anti-parallel diode forward current in Amps (A).
  • Points with subscripts greater than the BD_NSEG parameter are ignored.
VD1 IBD1 1.123456789
VD2 IBD2 1.123456789
VD3 IBD3 1.123456789
VD4 IBD4 1.123456789
VD5 IBD5 1.123456789
VD6 IBD6 1.123456789

Capacitor Models

Capacitors are modeled in SIMPLIS with Piece-Wise Linear capacitors.

  • A system of point-pairs is used with the X-Y plane defined with Voltage on the X-axis and Charge on the Y-axis.
  • A system of subscripts is used to define the point pairs. For example, VCCE0 and QCCE0 represent the lowest Voltage-Charge pair for the CCE capacitor with increasing subscripts representing increasing VCE voltages.
  • On the Voltage-Charge plane, the capacitance is the slope of any segment.
  • The actual number of segments is controlled by the CXX_NSEG, where "xx" is the capacitor GE, CE, or CG. The model uses only the number of point-pairs defined by CXX_NSEG; higher numbered point-pairs ignored.

Gate-Emitter Capacitor Model

Parameter Names Default Value Description
CGE_NSEG   1 Number of segments in the Gate-Emitter capacitor model
VCGE0 QCGE0 1.123456789 X-Y point definitions for CGE:
  • X-axis is the gate-emitter voltage in volts (V).
  • Y-axis is the capacitor charge (C).
  • Points with subscripts greater than the CGE_NSEG parameter are ignored.
VCGE1 QCGE1 1.123456789
VCGE2 QCGE2 1.123456789
VCGE3 QCGE3 1.123456789
VCGE4 QCGE4 1.123456789
VCGE5 QCGE5 1.123456789
VCGE6 QCGE6 1.123456789
VCGE7 QCGE7 1.123456789
VCGE8 QCGE8 1.123456789
VCGE9 QCGE9 1.123456789
VCGE10 QCGE10 1.123456789

Collector-Emitter Capacitor Model

Parameter Names Default Value Description
CCE_NSEG   4 Number of segments in the Collector-Emitter capacitor model
VCCE0 QCCE0 1.123456789 X-Y point definitions for CCE:
  • X-axis is the Collector-Emitter voltage in volts (V).
  • Y-axis is the capacitor charge (C).
  • Points with subscripts greater than the CCE_NSEG parameter are ignored.
VCCE1 QCCE1 1.123456789
VCCE2 QCCE2 1.123456789
VCCE3 QCCE3 1.123456789
VCCE4 QCCE4 1.123456789
VCCE5 QCCE5 1.123456789
VCCE6 QCCE6 1.123456789
VCCE7 QCCE7 1.123456789
VCCE8 QCCE8 1.123456789
VCCE9 QCCE9 1.123456789
VCCE10 QCCE10 1.123456789

Collector-Gate Capacitor Model

Parameter Names Default Value Description
CCG_NSEG   4 Number of segments in the Collector-Gate capacitor model
VCCG0 QCCG0 1.123456789 X-Y point definitions for CCG:
  • X-axis is Collector-to-gate voltage in volts (V).
  • Y-axis is charge in coulombs (C).
  • Points with subscripts greater than the CCG_NSEG parameter are ignored.
VCCG1 QCCG1 1.123456789
VCCG2 QCCG2 1.123456789
VCCG3 QCCG3 1.123456789
VCCG4 QCCG4 1.123456789
VCCG5 QCCG5 1.123456789
VCCG6 QCCG6 1.123456789
VCCG7 QCCG7 1.123456789
VCCG8 QCCG8 1.123456789
VCCG9 QCCG9 1.123456789
VCCG10 QCCG10 1.123456789