The modeling and the equations used in the NLB components are not compatible with the POP analysis. Hence the POP analysis and the AC analysis, which depends on the successful conclusion of the POP analysis, are both disabled when NLB components are present. Both the PWM Multipliers and PWL Multipliers are compatible with the POP and AC analyses.
The NLB components implement multiply and divide functions. Multipliers and Dividers are available with various input combinations described in the next table. In each model name, NLB_MULTIx_DIVy means the output of the particular component is normally equal to the product of x number of inputs in the numerator divided by the product of y number of inputs in the denominator.
The inputs and output of these multipliers and dividers must be positive with respect to the REF pin. Four quadrant versions of the NLB multiplier can be found here: Non-Linear 4-Quadrant (NLB) Multipliers
In this topic:
Model Name: | Non-Linear Multiplier/Divider | |
Simulator: | This device is compatible with the SIMPLIS simulator | |
Parts Selector Menu Location: |
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Symbol Library: | SIMPLIS_NLB.sxslb | |
Model File: | SIMPLIS_NLB.lb | |
Symbol Names: |
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Subcircuit Names: |
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Example Symbol: | ||
Multiple Selections: | Only one POP Trigger device is permitted on a schematic. |
To configure the NLB Multiplier/Divider, follow these steps:
Parameter Label | Units | Description |
Gain | The gain, as applied to the output of the multiplier. | |
Output high voltage limit | V | The maximum voltage allowed at the output pin. The output is limited to voltages less than this parameter value or the instantaneous voltage on the HLIM pin, which ever is less. |
Output low voltage limit | V | The minimum voltage allowed at the output pin. The output is limited to voltages greater than this parameter value or the voltage on the REF pin, which is normally zero volts, whichever is greater. |
Frequency of low-pass filter | Hz | Each NLB block has a low pass filter, with the corner frequency of the filter set by this parameter. |
Initial condition | V | The initial condition of the output in volts. |
Exponent of numerator input #n | The exponent applied the nth
numerator input. Each numerator can have exponents of
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Exponent of denominator input #n | The exponent applied the nth
denominator input. Each denominator can have exponents of
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Each non linear block multiplier/divider have the following attributes:
In addition to the common attributes of all multipliers and dividers, each input signal can be raised to be raised to the power of:
to compute the output voltage For example, if an 2 Multiplicand and 2 Divisor Multiplier is configured as follows:
the following mathematical equation is implemented:
\[ \text{1.2345} \times \frac{V_{N1} \times \sqrt{V_{N2}}}{V_{D1}^2 \times V_{D2}} \]
where VN1 and VN2 are the voltage of the “numerator” input pins N1 and N2 with respect to the reference pin, respectively, and VD1 and VD2 are the voltage of the “denominator” input pins D1 and D2 with respect to the reference pin, respectively. Since raising a negative number to non-integral powers is undefined, the signal is considered to be zero when such conditions occur. Hence, in this example, if VN2 is less than zero, the output of the particular NLB component is set to zero
This multiplier/divider implements the multiplier block used in the UC3854 PFC controller.
\[\frac{\left(A-1 \right) \times B}{C^2}\]
The B input of the UC3854 multiplier/divider component corresponds to the IAC input of the UC3854 PFC controller. Although the IAC input of UC3854 is a current-sensing input, the B input of the UC3854 multiplier/divider is a voltage-sensing input like any other input pins in the entire family of NLB components. Hence, the user needs to be aware of such differences in using the UC3854 multiplier/divider component to model any PFC controller similar to the UC3854 controller.
Four quadrant versions of the NLB multiplier can be found here: Non-Linear 4-Quadrant (NLB) Multipliers
Normally, simulation involving the NLB components would run at simulation speeds typical of a SIMPLIS simulation. The simulation speed time would increase tremendously if one of the “denominator” inputs is either very close to zero, or making either a positive-to-negative transition or a negative-to-positive transition. Proper limiting of the “denominator” inputs may eliminate such a slow simulation.