SIMetrix Verilog-A vs LRM 2.4

In the following we have highlighted areas where the SIMetrix Verilog-A compiler is not compliant with the LRM 2.4 standard.

In this topic:

2.7 String Literals

String variables are not supported.

2.9 Attributes

Attributes are supported for variables, parameters and module declarations.

3.4.2 Parameters - Value Range Specification

Only the first from specification will be functional. Subsequent exclude specifications will be accepted by the compiler but will have no effect.

3.4.3 Parameter Units and Descriptions

Syntax for "desc" and "units" is recognised but non-functional.

Non-standard SIMetrix attribute "instance" has been implemented. This defines the parameter as an instance parameter, that is, its value can be set on the device line. See Instance Parameters. Domain Binding

Anything other than "domain continuous" will raise an error. Natureless Disciplines and Domainless Disciplines

Implemented but non-functional Disciplines of Nets and Undeclared Nets

Not supported User Defined Attributes

Accepted but non-functional Net Descriptions

Not implemented. This will lead to a syntax error if used. Net Discipline Initial (Nodeset) Values

Not implemented. This will lead to a syntax error if used.

3.6.5 Implicit Nets

Not meaningful as hierarchical structures are not yet implemented.

3.7 Real Net Declarations

Not supported in Verilog-A

3.8 Default Discipline

Not supported in Verilog-A

3.9 Disciplines of primitives

Not supported in Verilog-A

3.10 Discipline Precedence

Not meaningful as hierarchical structures are not yet implemented.

3.11 Net compatibility

As hierarchical structures are not yet implemented, this is mostly not relevant.

But this is partially implemented within the simulator. If you connect different disciplines together you will get a warning. But the inherited disciplines will not be compatible, only the same disciplines may be inter-connected. ... and you only get a warning not an error.

3.12 Branches

Compliant for scalars only. Currently named vector branches are not supported. Unnamed branches are however fully supported.

Discipline compatibility is checked, but it seems that the discipline for each node in a branch must be identical. The spec requires them to be 'compatible' which is not the same thing.

Minor issue: if a branch is unused then the discipline of each node will not be checked at all and no error will be raised if they are incompatible. This is not defined in the standard.

4.2.6 Case Equality Operator

Not supported in Verilog-A

4.2.13 Concatenations

Not supported

4.2.14 Assignment Patterns

Simple assignment patterns are supported. Replication multiplier is not supported.

4.3 Built-in Mathematical Functions

Currently the Verilog-HDL versions of standard functions which start with a '$' are not supported.

4.5.15 Restrictions on Analog Operators

SIMetrix Verilog-A is mostly compliant with this section with the exception detailed below.

Analog operators (such as ddt, transition etc) are not allowed in places where their execution could be dependent on values that change during the course of a simulation. This is because analog operators store state information which could become invalid. SIMetrix does not always implement this restriction correctly and there are situation where it will allow you to use an analog operator but shouldn't.

4.5.3 Time derivative Operator

Compliant except tolerance is currently ignored.

4.5.4 Time integral operator

Fully implemented except abstol and nature parameters. These parameters are accepted but are non-functional.

4.5.5 Circular Integral Operators

Fully implemented except abstol and nature parameters. These parameters are accepted but are non-functional.

4.6.1 Analysis

Compliant except for "nodeset"

4.6.2 DC analysis

Compliant except for "nodeset" noise_table

Not implemented noise_table_log

Not implemented

4.7.1 Defining an Analog Function

Compliant except cannot use local parameters

4.7.2 Returning a Value from an Analog Function

Partially compliant. Can use return value for output. Output via passed argument is not supported. above Function

Not implemented absdelta Function

Not relevant for Verilog-A

6 Hierarchical Structures

In general, hierarchical structures are not supported by the SIMetrix Verilog-A implementation and this is the most significant feature omitted at this time. However, much of the functionality provided by this feature may be achieved via the netlist, so this should not impact on the usefulness of the compiler too much. We do intend to implement this in a future version.

This section of the standard does include the syntax for module definitions and this is of course fully supported. This is covered by the opening paragraphs of section 6.2. The rest of the section is not implemented.

7 Mixed Signal

Not implemented in Verilog-A

8 Scheduling Semantics

Most of this section is concerned with Verilog-AMS which is the mixed-signal version and so is not relevant.

9.6 Timescale system tasks

Not relevant for Verilog-A

9.7.1 $finish System Task

$finish compliant except argument to function is ignored

9.7.2 $stop System Task

$stop compliant except argument to function is ignored. $stop will cause the simulation to pause in the same way as clicking on the Pause button in the simulator status box. To resume after a call to $stop, click on the Resume button in the simulator status box or the equivalent menu.

9.7.3 $fatal, $error, $warning and $info System Task

Not implemented


Not relevant for Verilog-A


Not relevant for Verilog-A

9.10 Simulator time system functions

$abstime compliant. $realtime not supported and now deprecated


Not relevant for Verilog-A


Not relevant for Verilog-A

9.13.1 $random Function

Currently supports the LRM 2.2 specification with the first argument only. Version 2.4 LRM defines two functions, $random and $arandom. Refer to $random function for details about the SIMetrix implementation of the $random function.

9.13.2 Distribution Functions

Not supported

9.14 Math System Functions

Verilog-HDL versions of regular Verilog-A math functions. These are not currently supported but most functions can be used by simply removing the $ prefix.

9.15 Analog kernel parameter system functions

$temperature, $vt, $simparam compliant. $simparam$str is not supported

9.16 Dynamic simulation probe function

Not implemented

9.17.1 $discontinuity

Accepted but non-functional

9.17.2 $bound_step


9.17.3 $limit

Compliant using built-in "pnjlim". User functions not implemented.

9.18 Hierarchical System Parameter Functions

$mfactor implemented. Others are not

9.19 Explicit binding detection system functions

Both $param_given and $port_connected are compliant

9.20 Analog node alias system functions

Not implemented

9.21 Table Based Interpolation and Lookup System Function

Implementation is based on LRM 2.2 definition which supports linear interpolation only.


Not relevant for Verilog-A


Not relevant for Verilog-A

10 Compiler directives

These directives are compliant:

'define, 'else, 'endif, 'ifdef, 'include, 'undef

Predefined macros are not implemented

11, 12

Not implemented