In the following we have highlighted areas where the SIMetrix Verilog-A compiler is not compliant with the LRM 2.4 standard.
In this topic:
String variables are not supported.
Attributes are supported for variables, parameters and module declarations.
Only the first from specification will be functional. Subsequent exclude specifications will be accepted by the compiler but will have no effect.
Syntax for "desc" and "units" is recognised but non-functional.
Non-standard SIMetrix attribute "instance" has been implemented. This defines the parameter as an instance parameter, that is, its value can be set on the device line. See Instance Parameters.
Anything other than "domain continuous" will raise an error.
Implemented but non-functional
Not supported
Accepted but non-functional
Not implemented. This will lead to a syntax error if used.
Not implemented. This will lead to a syntax error if used.
Not meaningful as hierarchical structures are not yet implemented.
Not supported in Verilog-A
Not supported in Verilog-A
Not supported in Verilog-A
Not meaningful as hierarchical structures are not yet implemented.
As hierarchical structures are not yet implemented, this is mostly not relevant.
But this is partially implemented within the simulator. If you connect different disciplines together you will get a warning. But the inherited disciplines will not be compatible, only the same disciplines may be inter-connected. ... and you only get a warning not an error.
Compliant for scalars only. Currently named vector branches are not supported. Unnamed branches are however fully supported.
Discipline compatibility is checked, but it seems that the discipline for each node in a branch must be identical. The spec requires them to be 'compatible' which is not the same thing.
Minor issue: if a branch is unused then the discipline of each node will not be checked at all and no error will be raised if they are incompatible. This is not defined in the standard.
Not supported in Verilog-A
Not supported
Simple assignment patterns are supported. Replication multiplier is not supported.
Currently the Verilog-HDL versions of standard functions which start with a '$' are not supported.
SIMetrix Verilog-A is mostly compliant with this section with the exception detailed below.
Analog operators (such as ddt, transition etc) are not allowed in places where their execution could be dependent on values that change during the course of a simulation. This is because analog operators store state information which could become invalid. SIMetrix does not always implement this restriction correctly and there are situation where it will allow you to use an analog operator but shouldn't.
Compliant except tolerance is currently ignored.
Fully implemented except abstol and nature parameters. These parameters are accepted but are non-functional.
Fully implemented except abstol and nature parameters. These parameters are accepted but are non-functional.
Compliant except for "nodeset"
Compliant except for "nodeset"
Not implemented
Not implemented
Compliant except cannot use local parameters
Partially compliant. Can use return value for output. Output via passed argument is not supported.
Not implemented
Not relevant for Verilog-A
In general, hierarchical structures are not supported by the SIMetrix Verilog-A implementation and this is the most significant feature omitted at this time. However, much of the functionality provided by this feature may be achieved via the netlist, so this should not impact on the usefulness of the compiler too much. We do intend to implement this in a future version.
This section of the standard does include the syntax for module definitions and this is of course fully supported. This is covered by the opening paragraphs of section 6.2. The rest of the section is not implemented.
Not implemented in Verilog-A
Most of this section is concerned with Verilog-AMS which is the mixed-signal version and so is not relevant.
Not relevant for Verilog-A
$finish compliant except argument to function is ignored
$stop compliant except argument to function is ignored. $stop will cause the simulation to pause in the same way as clicking on the Pause button in the simulator status box. To resume after a call to $stop, click on the Resume button in the simulator status box or the equivalent menu.
Not implemented
Not relevant for Verilog-A
Not relevant for Verilog-A
$abstime compliant. $realtime not supported and now deprecated
Not relevant for Verilog-A
Not relevant for Verilog-A
Currently supports the LRM 2.2 specification with the first argument only. Version 2.4 LRM defines two functions, $random and $arandom. Refer to $random function for details about the SIMetrix implementation of the $random function.
Not supported
Verilog-HDL versions of regular Verilog-A math functions. These are not currently supported but most functions can be used by simply removing the $ prefix.
$temperature, $vt, $simparam compliant. $simparam$str is not supported
Not implemented
Accepted but non-functional
Compliant
Compliant using built-in "pnjlim". User functions not implemented.
$mfactor implemented. Others are not
Both $param_given and $port_connected are compliant
Not implemented
Implementation is based on LRM 2.2 definition which supports linear interpolation only.
Not relevant for Verilog-A
Not relevant for Verilog-A
These directives are compliant:
'define, 'else, 'endif, 'ifdef, 'include, 'undef
Predefined macros are not implemented
Not implemented
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