Hello World!

It has become customary to introduce any computer language with a "Hello world" program. That is a program that simply prints "Hello World!". While Verilog-A was not designed to perform this type of task, it is nevertheless possible to write such a program. Here is an example: 

module hello_world ;

analog
begin

@(initial_step)
$strobe("Hello World!") ;
end
endmodule

You can try this using the following procedure:

  1. Open a new Verilog-A design using menu File > New Verilog-A then enter the lines above. (This will copy and paste from the PDF OK, but be aware that in general copying and pasting ASCII text from PDFs can result in strange problems. In particular, watch out for '-' characters. These aren't always what they seem.)
  2. Save to a file called hello_world.va
  3. Open an empty schematic sheet.
  4. Save the schematic to any file name.
  5. Select menu Verilog-A > Construct Verilog-A Symbol
  6. Navigate to the file you created in step 2 above
  7. Select OK
  8. Place symbol that is created. It's just a box with no pins
  9. Setup a transient analysis with any stop time you like
  10. Run simulation

The first time you run this, you will see messages relating to the compilation procedure. After that the message "Hello World!" will be displayed in the command shell.

If you get any error messages, check the code you entered. The error message should point to the line where the problem occurred. Be aware that sometimes the line number given may not be exact. The point where the parser detects that something is wrong may occur one or two lines after the actual cause of the problem. For example, if you omitted the ';' on the line containing the $strobe call, you would see the error "Unexpected token 'end'" error reported for the following line or possibly even the line after that. The 'end' token would not be expected if the ';' was missing but this is on the next line.

Although our hello world program does not do much, it does introduce a number of Verilog-A concepts:

  1. Modules. All devices that can be instantiated as models and instances are defined as modules. In the above example the module has the name hello_world. This name is used in the associated .MODEL statement in the SIMetrix netlist to access this module.
  2. The analog block denoted by the keyword analog. This is where the main body of the Verilog-A definition is placed
  3. Initial step event denoted by @(initial_step). The statement following this will be executed only in the first step of the simulation, that is, the dc operating point phase. You might like to see what happens if you remove this line. You can do this easily by 'commenting it out' which can be done with to forward slashes like this: 
    //@(initial_step)
  4. $strobe. This is known as a system task in the Verilog-A LRM (language reference manual). $strobe outputs a message to the command shell. It can also output values in various formats and behaves in a similar way to the 'C' printf function. We will see more of this later.

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