Exclusive OR Gate

In this topic:

  • Netlist entry
  • Connection details
  • Model format
  • Model parameters
  • Device Operation

    • Netlist entry

    Axxxx [ in_0 in_1 .. in_n ] out model_name

    Connection details

    Name Description Flow Type Vector bounds
    in Input in d, vector 2−∞
    out Output out d n/a

    Model format

    .MODEL model_name d_xor parameters

    Model parameters

    Name Description Type Default Limits
    rise_delay Rise delay real 1nS 1e−12−∞
    fall_delay Fall delay real 1nS 1e−12−∞
    input_load Input load value (F) real 1pF none
    family Logic family string UNIV none
    in_family Input logic family string UNIV none
    out_family Output logic family string UNIV none
    out_res Digital output resistance real 100 0−∞
    out_res_pos Digital output res. pos. slope real out_res 0−∞
    out_res_neg Digital output res. neg. slope real out_res 0−∞
    open_c Open collector output boolean FALSE none
    min_sink Minimum sink current real -0.001 none
    max_source Maximum source current real 0.001 none
    sink_current Input sink current real 0 none
    source_current Input source current real 0 none

    Device Operation

    • If the OPEN_C parameter is FALSE, the output is at logic '1' if an odd number of inputs are at logic '1'. If any input is UNKNOWN the output will be UNKNOWN, otherwise the output will be at logic '0'.
    • If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If an odd number of inputs are at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. If any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.
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