Non-linear Transfer Function

Expression

The expression entered defines the output of the device in terms of its inputs. Expressions generally comprise the following elements:

Circuit Variables

Circuit variables allow the expression to reference input voltages and currents.

Voltages are of the form:

V(node_name1)

V(node_name1, node_name2)

Where node_name1 and node_name2 are input connections.The second form above returns the difference between the voltages on node_name1 and node_name2. The special names out, outp and outn may be used to access the voltage on the output. Use out for the single ended output configuration and outp and/or outn for the differential output configuration.

Currents are of the form:

I(source_name)

Where source_name is the name of an input current. For output voltage configurations, you can use I(out) to access the output current of the device itself. For example

100*I(OUT)

Implements a 100 ohm resistor for a device configured with a differential output voltage.

Parameters

The expression may use any number of parameters. These can be local or global. Local parameters are defined in the Local parameters edit box on the right hand side. Global parameters must defined within the schematic, usually in the F11 window.

To enter local parameters, enter one or more definitions in the form name=expression in the Local parameters edit box. expression may be a constant or an expression referring to other local or global parameters. expression may not contain circuit variables. (E.g. V(in1)). Comment lines may be entered and must start with a '*'.

Built-in Parameters

A number of parameter names are assigned by the simulator. These are:

Constants

Apart from simple numeric values, arbitrary expressions may also contain the following built-in constants:

Operators

These are listed below and are listed in order of precedence. Precedence controls the order of evaluation. So 3*4 + 5*6 = (3*4) + (5*6) = 42 and 3+4*5+6 = 3 + (4*5) + 6 = 29 as '*' has higher precedence than '+'.

Comparison, Equality and Logical Operators

These are Boolean in nature either accepting or returning Boolean values or both. A Boolean value is either TRUE or FALSE. FALSE is defined as equal to zero and TRUE is defined as not equal to zero. So, the comparison and equality operators return 1.0 if the result of the operation is true otherwise they return 0.0.

The arguments to equality operators should always be expressions that can be guaranteed to have an exact value e.g. a Boolean expression or the return value from functions such as SGN. The == operator, for example, will return TRUE only if both arguments are exactly equal. So the following should never be used:

v(n1)==5.5

v(n1) may not ever be exactly 5.0. It may be 5.4999999999 or 5.50000000001 but only by chance will it be 5.5.

These operators are intended to be used with the IF() function described in Ternary Conditional Expression.

Digital Operators

These are the operators '&', '|' and '~'. These are now considered to be obsolete and may not be supported in future versions of SIMetrix. These operators implement logic operations in the analog domain and are continuous in nature.

Ternary Conditional Expression

This is of the form:

test_expression ? true_expression : false_expression

The value returned will be true_expression if test_expression resolves to a non-zero value, otherwise the return value will be false_expression. This is functionally the same as the IF() function described in the functions table below.

Functions

Monte Carlo Distribution Functions

The following functions return a randomly generated value when running a Monte Carlo analysis. They can be used to define component tolerances.

A full discussion on the use of Monte Carlo distribution functions is given in Simulator Reference Manual/Monte Carlo, Sensitivity and Worst-case/Specifying Tolerances.

IF() Function

IF(condition, true-value, false-value[, max-slew])

if condition is non-zero, result is true-value, else result is false-value.

If max-slew is present and greater than zero, the result will be slew-rate limited in both positive and negative directions to the value of max-slew.

In some situations, for example if true-value and false-value are constants, the result of this function will be discontinuous when condition changes state. This can lead to non-convergence as there is no lower bound on the time-step. In these cases a max-slew parameter can be included. This will limit the slew rate so providing a controlled transition from the true-value to the false-value and vice-versa.

If the simulator setting .OPTIONS DISCONTINUOUSIFSLEWRATE=max-slew, is provided, SIMetrix will automatically apply a max-slew parameter to all occurrences of the IF() function if both true-value and false-value are constants. This provides a convenient way of resolving convergence issues with third-party models that make extensive use of discontinuous if expressions. Note that the DISCONTINUOUSIFSLEWRATE option is also applied to conditional expressions using the C-style condition ? true-value : false-value syntax.

LIMITS() Function

LIMITS(x, low, high, sharp)

The LIMITS function follows this equation:

LIMITS(x, low, high, sharp) = ???MATH???0.5*((\ln(\cosh(v1))-\ln(\cosh(v2)))/v3 +(low+high))???MATH???

Look-up Tables

Method 1 is more efficient at handling large tables (hundreds of values). However, method 2 is generally more flexible and is the recommended choice for most applications. Method 2 is also compatible with other simulators whereas method 1 is proprietary to SIMetrix.

For an example see Table Lookup Example

Examples

Table Lookup Example

The following arbitrary source definition implements a soft limiting function

table[-10, -5, -5, -4, -4, -3.5, -3, -3, 3, 3, 4, 3.5, 5, 4, 10, 5](v(N1))

TABLE(v(N1), -10, -5, -5, -4, -4, -3.5, -3, -3, 3, 3, 4, 3.5, 5, 4, 10, 5)

TABLEX(v(N1), -10, -5, -5, -4, -4, -3.5, -3, -3, 3, 3, 4, 3.5, 5, 4, 10, 5)

The resulting transfer functions are illustrated in the following picture:

Verilog-A Implementation

If you have SIMetrix Pro or SIMetrix Elite you may select the Compile to binary using Verilog-A option. This will build a definition of the device using the Verilog-A language then compile it to a binary DLL. This process takes place when you run the simulation. The benefit of using Verilog-A is that there is a wider range of functions available and for complex definitions there will also be a performance benefit. Refer to the Verilog-A Manual for details of available functions.