Hysteresis Block

This is a simple design that demonstrates using state variables. The clock has a single input and a single output. When the input exceeds 3V the output switches to a high state. When the input falls below 2V the output switches to a low state. As the state of the switch cannot be unambiguously determined from the input, the Verilog-A code uses an integer variable to store the state of the switch.

'include "disciplines.vams"

module hysteresis_block(vc, out) ;

electrical vc, out ;

integer state ;
real vout ;

parameter real HIGH=5.0 ;
parameter real LOW= 0.0 ;

analog initial
state = 1 ;

analog
begin

@(cross(V(vc)-3,1))
state=1 ;
@(cross(V(vc)-2,-1))
state=0 ;

if (state==1)
vout = HIGH ;
else
vout = LOW ;

V(out) <+ transition(vout, 0, 1n, 1n) ;
end

endmodule

The state variable in the above is the integer state. There is nothing in the code that declares the variable as a state variable; the Verilog-A compiler detects this automatically. The two cross event statements set state when the input passes the desired thresholds. The analog initial block is used to set the starting state. For simplicity, this is set to 1.