When running a simulation, you will see a number of messages in the command shell. These are output by the Verilog-A compiler and the MAKE utility.
In rare cases, there may be warnings or errors generated by the 'C' compliler or linker. These should be reported to technical support.
Errors or warning output by the Verilog-A compiler will be displayed during this process.These will be in the form:
*** ERROR *** (@'verilog-a-filename',linenum), error-message
If the problem is with the syntax, the message will say *** SYNTAX ERROR ***.
NOTE: Identifiers that you use in your Verilog-A code (e.g. variables, parameters, ports etc) may be prefixed with an underscore when referenced in any warning or error message.
When you run a .VA file for the second and subsequent time without editing it, you will not see any messages from the Verilog-A compiler.
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