Set-Reset Flip-Flop

In this topic:

  • Netlist entry
  • Connection details
  • Model format
  • Model parameters
  • Device Operation

    • Netlist entry

    Axxxx s r clk set reset out nout model_name

    Connection details

    Name Description Flow Type
    s S input in d
    r R input in d
    clk Clock in d
    set Asynchronous set in d
    reset Asynchronous reset in d
    out Data output out d
    nout Inverted data output out d

    Model format

    .MODEL model_name d_srff parameters

    Model parameters

    Name Description Type Default Limits
    clk_delay Delay from clk real 1nS 1e−12−∞
    set_delay Delay from set real 1nS 1e−12−∞
    reset_delay Delay from reset real 1nS 1e−12−∞
    ic Output initial state integer 0 0 - 2
    rise_delay Rise delay real 1nS 1e−12−∞
    fall_delay Fall delay real 1nS 1e−12−∞
    sr_load S,r load values (F) real 1pF none
    clk_load Clk load value (F) real 1pF none
    set_load Set load value (F) real 1pF none
    reset_load Reset load value (F) real 1pF none
    family Logic family string UNIV none
    in_family Input logic family string UNIV none
    out_family Output logic family string UNIV none
    out_res Digital output resistance real 100 0−∞
    out_res_pos Digital output res. pos. slope real out_res 0−∞
    out_res_neg Digital output res. neg. slope real out_res 0−∞
    open_c Open collector output boolean FALSE none
    min_sink Minimum sink current real -0.001 none
    max_source Maximum source current real 0.001 none
    sink_current Input sink current real 0 none
    source_current Input source current real 0 none

    Device Operation

    The SR flip flop is similar to a JK flip flop except that the output is UNKNOWN when both S and R inputs are high. In a JK the output toggles in the same circumstances.

    The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge on the clock.

    S input R input Output
    0 0 No change
    0 1 0
    1 0 1
    1 1 UNKNOWN
    When either input is UNKNOWN, the situation is more complicated. There are some circumstances when a known state can be clocked to the output even if one of the inputs is unknown. The following table describes the operation for possible input states. X means UNKNOWN.
    S input R input old output new output
    0 0 0 0
    0 0 1 1
    0 0 X X
    0 1 0 0
    0 1 1 0
    0 1 X 0
    0 X 0 0
    0 X 1 X
    0 X X X
    1 0 0 1
    1 0 1 1
    1 0 X 1
    1 1 0 X
    1 1 1 X
    1 1 X X
    1 X 0 X
    1 X 1 X
    1 X X X
    X 0 0 X
    X 0 1 1
    X 0 X X
    X 1 0 X
    X 1 1' X
    X 1 X X
    X X 0 X
    X X 1 X
    X X X X
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