Toggle Flip Flop

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Netlist entry

Axxxx t clk set reset out nout model_name

Connection details

Name Description Flow Type
t Toggle input in d
clk Clock in d
set Asynchronous set in d
reset Asynchronous reset in d
out Data output out d
nout Inverted data output out d

Model format

.MODEL model_name d_tff parameters

Model parameters

Name Description Type Default Limits
clk_delay Delay from clk real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
set_delay Delay from set real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
reset_delay Delay from reset real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
ic Output initial state integer 0 0 - 2
rise_delay Rise delay real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
fall_delay Fall delay real 1nS ???MATH???1\text{e}^{-12} - \infty???MATH???
t_load Toggle load value (F) real 1pF none
clk_load Clk load value (F) real 1pF none
set_load Set load value (F) real 1pF none
reset_load Reset load value (F) real 1pF none
family Logic family string UNIV none
in_family Input logic family string UNIV none
out_family Output logic family string UNIV none
out_res Digital output resistance real 100 ???MATH???0 - \infty???MATH???
out_res_pos Digital output res. pos. slope real out_res ???MATH???0 - \infty???MATH???
out_res_neg Digital output res. neg. slope real out_res ???MATH???0 - \infty???MATH???
min_sink Minimum sink current real -0.001 none
max_source Maximum source current real 0.001 none
sink_current Input sink current real 0 none
source_current Input source current real 0 none

Device Operation

The operation of the toggle flip flop is illustrated by the following diagrams. When the T input is high, the output toggles on each rising edge of the clock. If the T input is UNKNOWN the output will be UNKNOWN.

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