SIMetrix Verilog-A vs LRM 2.2

In the following we have highlighted areas where the SIMetrix Verilog-A compiler is not compliant with the LRM 2.2 standard.

In this topic:

2.6 Strings

String variables are not supported. This is compliant with the Annex C 'Analog Language Subset'


desc and units attributes may be included but will not be functional.

3.2.2 Parameters - Value Range Specification

Only the first from specification will be functional. Subsequent exclude specifications will be accepted by the compiler but will have no effect.

3.2.3 Parameter Units and Descriptions

Syntax for "desc" and "units" is recognised but non-functional.

Non-standard SIMetrix attribute "instance" has been implemented. This defines the parameter as an instance parameter, that is, its value can be set on the device line. See Instance Parameters. Domain Binding

Anything other than "domain continuous" will raise an error. Empty Disciplines

Implemented but non-functional Disciplines of Wires and Undeclared Nets

Not supported User Defined Attributes

Accepted but non-functional Net Descriptions

Not implemented. This will lead to a syntax error if used. Net Discipline Initial (Nodeset) Values

Not implemented. This will lead to a syntax error if used.

3.4.5 Implicit Nets

Not meaningful as hierarchical structures are not yet implemented.

3.5 Real Net Declarations

Not supported in Verilog-A

3.6 Default Discipline

Not supported in Verilog-A

3.7 Discipline Precedence

Not meaningful as hierarchical structures are not yet implemented.

3.8 Net compatibility

As hierarchical structures are not yet implemented, this is mostly not relevant.

But this is partially implemented within the simulator. If you connect different disciplines together you will get a warning. But the inherited disciplines will not be compatible, only the same disciplines may be inter-connected. ... and you only get a warning not an error.

3.9 Branches

Compliant for scalars only. Currently named vector branches are not supported. Unnamed branches are however fully supported.

Discipline compatibility is checked, but it seems that the discipline for each node in a branch must be identical. The spec requires them to be 'compatible' which is not the same thing.

Minor issue: if a branch is unused then the discipline of each node will not be checked at all and no error will be raised if they are incompatible. This is not defined in the standard.

4.1.6 Case Equality Operator

Not supported in Verilog-A

4.1.13 Concatenations

Array initialisers are supported. Replication multiplier is not supported.

4.2.3 Error Handling

Not correctly implemented.

Its possible that this may never be implemented to the letter of the standard. While attempting to iterate to convergence, it is not at all uncommon for maths functions to be overflow or to receive invalid arguments. When this happens, SIMetrix reduces the step (whatever that step may be) and tries again. This algorithm is often successful.

Complying with the most literal interpretation of this would be undesirable as it would mean some simulations failing when they may have been perfectly solveable.

4.4.1 Restrictions on Analog Operators

SIMetrix Verilog-A is mostly compliant with this section with the exception detailed below.

Analog operators (such as ddt, transition etc) are not allowed in places where their execution could be dependent on values that change during the course of a simulation. This is because analog operators store state information which could become invalid. SIMetrix does not always implement this restriction correctly and there are situation where it will allow you to use an analog operator but shouldn't.

4.4.4 Time derivative Operator

Compliant except tolerance is currently ignored.

4.4.5 Time integral operator

  • idt(expr) - compliant
  • idt(expr,ic) - compliant

Others not implemented.

4.4.6 Circular Intergral Operators

Not implemented.

4.4.13 Z-transform filters

Not implemented.

4.5.1 Analysis

Compliant except for "nodeset"

4.5.2 DC analysis

Compliant except for "nodeset" Noise_table

Not implemented

4.6.1 Defining an Analog Function

Compliant except cannot use local parameters

4.6.2 Returning a Value from an Analog Function

Partially compliant. Can use return value for output. Output via passed argument is not supported.

5.3.2 Indirect Branch Assignments

Not implemented

6.7.5. Above Function

Not implemented

7 Hierarchical Structures

In general, hierarchical structures are not supported by the SIMetrix Verilog-A implementation and this is the most siginicant feature omitted at this time. However, much of the functionality provided by this feature may be achieved via the netlist, so this should not impact on the usefulness of the compiler too much. We do intend to implement this in a future version.

This section of the standard does include the syntax for module definitions and this is of course fully supported. This is covered by the opening paragraphs of section 7.1. The rest of the section is not implemented.

8 Mixed Signal

Not implemented in Verilog-A

9 Scheduling Semantics

Most of this section is concerned with Verilog-AMS which is the mixed-signal version and so is not relevant.

10.1 Environment Parameter Functions

$realtime is not supported. All others are compliant.

10.2 $random Function

Supported for first argument only. 'type_string' argument is not supported.

10.2 $dist_ Functions

Not supported

10.4 Simulation Control System Tasks

Compliant except argument to functions are ignored.

10.7 Announcing Discontinuity

Accepted but doesn't actually do anything

10.9 Limiting Functions

Compliant using built-in "pnjlim". User functions not implemented.

10.10 Hierarchical System Parameter Functions

$mfactor implemented. Others are not

11.1 'default_discipline

Not implemented

11.2 'default_transition

Not implemented

11.6 'resetall

Not implemented

11.7 Pre-defined Macros

Not implemented

12, 13

Not implemented