Opens a Verilog-A source file in the text editor. This will apply syntax highlighting for the Verilog-A language.
OpenVerilogA <filename>
/encoding |
encoding. For details see documentation of second argument to LoadFile |
/fws |
File watcher status, enable|disable|auto |
filename |
Path of Verilog-A source file to open |
▲ Command Summary ▲ | ||
◄ OpenSimplisStatusBox | OpenVerilogHDL ▶ |