Device Models Used in Simplis

Piecewise-Linear Resistor Models

There are two acceptable model types for piecewise-linear resistors:

.MODEL  mname  mtype  NSEG=k  X0=x0  Y0=y0
+ X1=x1  Y1=y1  X2=x2  Y2=y2 ...  Xk=xk  Yk=yk

The slope of each line segment on the v-i plane is the differential conductance in Siemens for the device. The small-signal resistance is then the reciprocal of the differential conductance.

VPWLR -Type Model

The VPWLR model type is used for piecewise-linear v-i characteristics which are voltage-defined. In other words, the value of current is uniquely defined for every value of voltage. In such a case, the voltage-current coordinates at the points of definition of the v-i characteristics must satisfy the following two restrictions:

As an example, the diagram below shows the v-i characteristics of an ordinary pn-junction diode and that of a tunnel diode. It is apparent from the diagram that the characteristics of these two devices satisfy the voltage-defined requirement and each of these two devices can be modeled by a VPWLR-type piecewise-linear resistor.

4.1 The v-i characteristics of (a) an ordinary pn-junction diode and (b) a tunnel diode.

IPWLR -Type Model

The IPWLR model type is reserved for piecewise-linear v-i characteristics which are current-defined in the sense that the value of voltage is uniquely defined for every value of current. In such a case, the voltage-current coordinates at the points of definition of the v-i characteristics must satisfy the following restrictions:

For example, the v-i characteristics of the ordinary pn-junction diode shown in diagram 4.1(a) above and the v-i characteristics shown in diagram 4.2 can both be considered to behave as nonlinear current-defined resistors. Therefore, each can be approximated by an IPWLR-type model. On the other hand, the tunnel diode characteristics shown in diagram 4.1(b) cannot be modeled by an IPWLR-type model since the values for the branch voltage are not uniquely defined for every value of current. Similarly, the v-i characteristics shown in 4.2 cannot be modeled by a VPLWR-type model.

4.2 Example of a type of v-i characteristics that can be described as a current-defined resistor.

Piecewise-Linear Inductor and Capacitor Models

The model statements for piecewise-linear inductors and capacitors are very similar to those for the piecewise-linear resistors. In the case of a piecewise-linear resistor, its characteristics are defined in terms of points on the current vs voltage plane. In the case of a piecewise-linear inductor, the characteristics are defined in terms of points on the flux-linkage vs. current plane. In the case of a piecewise-linear capacitor, the characteristics are defined in terms of points on the charge vs voltage plane.

The model statement format for a piecewise-linear inductor or capacitor is:

.MODEL  mname  mtype  NSEG=k  X0=x0  Y0=y0
+ X1=x1  Y1=y1  X2=x2  Y2=y2 ...  Xk=xk  Yk=yk

\[ x0 < x1 < x2 < ... < xk \]

\[ y0 < y1 < y2 < ... < yk \]

Simple Switch Models

SIMPLIS accepts two types of simple switch models:

.MODEL  mname  mtype  RON=ron  ROFF=roff
+ TH=threshold  HYSTWD=hystwd  LOGIC={POS|NEG}

The diagram below defines the state of the simple switch, under two operating modes. If LOGIC is assigned the value POS, the switching of the simple switch is defined by (a). If LOGIC is assigned the value NEG, the switching logic is reversed, and the state of the simple switch is then defined by (b).

When a simple switch is in the closed state, it is modeled by a linear resistor having a resistance equal to ron between its positive node and negative node. When the simple switch is in the open state, the resistance of the linear resistor changes to roff.

4.3 State diagram of the simple switch when the parameter LOGIC is assigned a value of (a) POS or (b) NEG.

Simple Transistor Switch Models

There are four simple transistor models, composed of:

.MODEL  mname  mtype  VSAT=vsat  RSAT=rsat
+ ROFF=roff  GAIN=gain  TH=threshold
+ HYSTWD=hystwd  LOGIC={POS|NEG}  LEVEL={1|2}

For model types VCQPOS and ICQPOS, the voltage across the transistor switch, measured as the voltage of the positive node with respect to the voltage of the negative node, assumes nonnegative values under normal operation like an NPN bipolar transistor and an N-channel MOSFET. For model types VCQNEG and ICQNEG, the voltage across the transistor switch, measured as the voltage of the positive node with respect to the voltage of the negative node, assumes non positive values under normal operation like a PNP bipolar transistor and a P-channel MOSFET.

Models for Simple Transistor Switches for LEVEL=1

When a simple transistor switch is modeled with the LEVEL parameter set to 1, it can assume either an open or a closed state. The switching diagram in 4.3 (a) applies when LOGIC is set to POS while the switching diagram in 4.3 (b) applies when LOGIC is set to NEG.

The only difference between a simple switch and a simple transistor switch with LEVEL set to 1 is the model of the closed state. When a simple transistor switch with LEVEL set to 1 is in the closed state, it is modeled by a linear resistor with the value rsat in series with a constant voltage source with the value vsat. When the simple transistor switch is in the open state, it is modeled by a resistor with the value roff. The block diagram and the V-I characteristic of the model are shown in Figure 4.4. The circuit element model of the simple transistor switch with LEVEL set to 1 for the closed and open states are shown in diagram 4.4 below.

4.4 Model for the simple transistor switch: (a) Simple transistor switch controlled by a control signal cs(t), (b) the i Q vs v Q characteristic of the simple POS-type transistor switch, and (c) the i Q vs v Q characteristic of the simple NEG-type transistor switch.

4.5 Model for the simple transistor switch: (a) model of the simple transistor switch for LEVEL=1 when it is in a closed state, and (b) model of the simple transistor switch for LEVEL=1 when it is in an open state.

If a physical transistor is being driven to act like a switch and detailed waveforms of the voltage across the transistor and the current through the transistor are not critically important, it is recommended that such a transistor be modeled by a simple transistor switch with the parameter LEVEL set to 1 since the simulation is faster when a transistor switch has LEVEL set to 1.

When a simple transistor switch is modeled with the LEVEL parameter set to 1, the value of the GAIN parameter has no effect on the modeling. In addition, the direction of current flow through the transistor switch is not restricted and the device behaves more like a controlled switch than a physical transistor.

Models for Simple Transistor Switches for LEVEL=2

When a simple transistor switch is modeled with the LEVEL parameter set to 2, it still assumes either an open state or a closed state. The switching diagram in 4.3(a) still applies when LOGIC is set to POS while the switching diagram in 4.3 (b) still applies when LOGIC is set to NEG.

When the LEVEL parameter is set to 2, the simple transistor is still modeled by a resistor with a resistance equal to roff when it is in the open state. When the simple transistor switch is in the closed state, additional secondary states are provided for the simple transistor, allowing the modeling of a physical transistor at operating areas where both the voltage across and the current through the transistor are simultaneously substantial. For bipolar transistors, such operating areas are collectively called the active region. For the simple transistor switch the individual states are called ACTIVE, SATURATE, and REV_BIASED, to stand for active region, saturation, and reversed-biased, as indicated in 4.6 . SIMPLIS internally computes the voltage across and the current through the simple transistor switch to determine the correct secondary state at which the transistor switch should operate.

4.6 Model for the simple transistor switch for LEVEL=2. (a) A simple transistor switch controlled by a control signal cs(t), (b) The i Q vs v Q characteristics of a VCQPOS-type or ICQPOS-type transistor switch, (c) The i Q vs v Q characteristic of a VCQNEG-type or ICQNEG-type transistor switch.

When the secondary state of a simple transistor switch is equal to ACTIVE, it is modeled by a parallel combination of a linear resistor with a resistance equal to roff and a controlled-current source ci(t) as indicated in 4.7(a). The current ci(t) of the controlled-current source is defined by the following equations if LOGIC is set to POS:

ci(t) = gain * [cs(t) - (threshold - hystwd/2)]

for  VCQPOS-type transistor switches and
for  ICQPOS-type transistor switches

ci(t) = - gain * [ cs(t) - (threshold - hystwd/2) ]

for  VCQNEG-type transistor switches and
for  ICQNEG-type transistor switches.

ci(t) = - gain * [ cs(t) - (threshold + hystwd/2) ]

for  VCQPOS-type transistor switches and
for  ICQPOS-type transistor switches, and

ci(t) = gain * [ cs(t) - (threshold + hystwd/2) ]

for  VCQNEG-type transistor switches and
for  ICQNEG-type transistor switches.

When the secondary state of a simple transistor switch is equal to SATURATE, it is modeled by the small network as shown in 4.7(b), which comprises a linear resistor with a resistance equal to rsat in series with a voltage source with source value vsat. When the secondary state of a simple transistor switch is equal to REV_BIASED, it is modeled by a large resistor with resistance equal to roff as shown in 4.7 (c).

4.7 Model of a simple transistor switch in the closed state, with LEVEL=2. (a) Model for the ACTIVE secondary state, (b) Model for the SATURATE secondary state, (c) Model for the REV_BIASED secondary state.

By selecting LEVEL=2 in the simple transistor switch model, you can more accurately model a physical transistor and are able to obtain more detailed waveforms on the voltage and current for the device. The penalty is an increase in the simulation time since more variables need to be monitored and computed throughout the simulation.

Simple Logic Device Models

To aid the understanding of the models for simple logic devices, the concept of "positive" and "negative" logic is discussed first. Except for inverters and comparators, all logic gates use a parameter called LOGIC in the model statement. The purpose of this parameter is to define whether a "positive logic" or a "negative logic" convention is used in defining the logic states.

If the LOGIC parameter is set to POS, positive logic is used to determine the logic states of the inputs and the output. This means a state of logic 0 is represented by a lower voltage level than that of a state of logic 1. In this case, the input logic state of an input node is defined to be at logic 1 if

V(ni,nref) >= threshold + hystwd/2

The input logic state is considered to be at logic 0 if

V(ni,nref) <=  threshold - hystwd/2

If the LOGIC parameter is set to NEG, negative logic is used to determine the logic states of the inputs and the output. Negative logic means a state of logic 0 is represented by a higher voltage level than that of a state of logic 1. In this case, the input logic state of an input node ni is defined to be at logic 1 if

V(ni,nref) <= threshold - hystwd/2

V(ni,nref) >= threshold + hystwd/2

Inverter Model

The format for the inverter model statement is:

.MODEL  mname  INV  TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout

4.8 SIMPLIS inverter model: (a) Symbol for inverter, (b) Model for inverter. The nodes ni, no and nref are the input, output and the reference nodes, respectively.

If the output state of an inverter is equal to logic 1, the value of the voltage source, vout, in the output circuit is set to voh. In this case, the output state of the device is changed to logic 0 when

V(ni,nref) >= threshold + hystwd/2

If the output state of an inverter is equal to logic 0, the value of the voltage source, vout, in the output circuit is set to vol. In this case, the output state of the device is changed to logic 1 when

V(ni,nref) <=  threshold - hystwd/2

Comparator Model

The format for the comparator model statement is:

s.MODEL  mname  COMP HYSTWD=hystwd  VOL=vol  VOH=voh
+ RIN=rin  ROUT=rout

4.9 SIMPLIS comparator model: (a) Symbol for comparator, (b) Model for comparator. The nodes n1, n2 are the two input nodes. The nodes no and nref are the output and reference nodes, respectively.

If the output state of a comparator is equal to logic 1, the value of the voltage source, vout, in the output circuit is set to voh. In this case, the output state of the device is changed to logic 0 when

V(ni1,ni2) <= - hystwd/2

If the output state of a comparator is equal to logic 0, the value of the voltage source, vout, in the output circuit is set to vol. In this case, the output state of the device is changed to logic 1 when

V(ni1,ni2) >= hystwd/2

Exclusive-OR Gate Model

The format for the Exclusive-OR model statement is:

.MODEL  mname  XOR TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}

4.10 Exclusive-OR gate model: (a) Symbol for exclusive-OR gate, (b) Model for exclusive-OR gate. The nodes ni1 and ni2 are the two input nodes. The nodes no and nref are the output and reference nodes, respectively.

The actual model implemented in SIMPLIS for an exclusive-OR gate is shown in 4.10 (a). The source value of the voltage source, vout, in the output circuit depends on the logic state of the output of the gate. The output state is equal to the result of the boolean EXCLUSIVE-OR operation on the two input states.

OR Gate Model

The format for the OR Gate model statement is:

.MODEL mname  ORk TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}

4.11 k-Input OR gate model: (a) Symbol for k-Input OR gate, (b) Model for k-Input OR gate. The nodes ni1 and ni2 are the two input nodes. Up to a maximum of 9 inputs can be accommodated.

The actual model implemented in SIMPLIS for a k-input OR gate is shown in 4.11 (b). The output state is equal to the result of the boolean OR operation applied to the k input states.

NOR Gate Model

The format for the NOR Gate model statement is:

.MODEL mname NORk TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}

AND Gate Model

The format for the AND Gate model statement is:

.MODEL mname ANDk TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}

NAND Gate Model

The format for the NAND gate model statement is:

.MODEL mname NANDk TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}

where

Set-Reset Flip Flop Model

The format for the Set-Reset flip flop model statement is:

.MODEL mname SRFF TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}

where

The logic state of the output Q' is always equal to the logical complement of the logic state of the output Q. The initial condition specified in the device statement for an S-R flip-flop is used to initialize the logic output state of the normal output Q. When the logic state of the set input is equal to logic 1, the logic state of the normal output Q is set to logic 1. When the logic state of the reset input is equal to logic 1, the logic state of the normal output Q is set to logic 0.

The output state of an S-R flip flop is supposed to be undefined when the input logic states of the set and reset inputs are both equal to logic 1. For ease of debugging, the output state of the S-R flip-flop as implemented by SIMPLIS will remain unchanged when both input states are equal to logic 1. (See 4.12)

4.12 SR Flip Flop model: (a) Symbol for a SIMPLIS S-R flip flop, (b) Model for a SIMPLIS S-R flip flop.

Clocked Set-Reset Flip-Flop

.MODEL mname CLK_SRFF TH=threshold
+ HYSTWD=hystwd  VOL=vol  VOH=voh  RIN=rin
+ ROUT=rout  LOGIC={POS | NEG}
+ TRIG_COND={0_TO_1 | 1_TO_0}

If TRIG_COND = 0_TO_1, the clocked Set-Reset flip-flop is considered to be "triggered" when the logic state of the clock input changes from 0 to 1. Similarly, a logic 1 to logic 0 transition for the clock input is considered to "trigger" this type of flip-flop if TRIG_COND = 1_TO_0. The logic state of each output will not change except at the triggering moment. At the triggering moment, the logic of the clocked Set-Reset flip-flop is same as that of the unclocked Set-Reset flip-flop.

4.13 Clocked SR Flip Flop model: (a) Symbol for a SIMPLIS Clocked S-R flip flop, (b) Model for a SIMPLIS Clocked S-R flip flop.

Clocked J-K Flip-Flop

.MODEL mname CLK_JKFF TH=threshold
+ HYSTWD=hystwd  VOL=vol  VOH=voh  RIN=rin+ ROUT=rout  LOGIC={POS | NEG}
+ TRIG_COND={0_TO_1 | 1_TO_0}

If TRIG_COND = 0_TO_1, the clocked J-K flip-flop is considered to be "triggered" when the logic state of the clock input changes from 0 to 1. Similarly, a logic 1 to logic 0 transition for the clock input is considered to "trigger" this type of flip-flop if TRIG_COND = 1_TO_0. The logic state of each output will not change except at the triggering moment. At the triggering moment, the logic of the clocked J-K flip-flop is same as that of the unclocked Set-Reset flip-flop with one exception: if the states of both the J and the K inputs are equal to logic 1 at the triggering moment, the states of each output of a clocked J-K flip-flop will be set to the complement of its logic state right before the triggering moment. Hence, if the state of the normal output Q is equal to logic 1/0 right before the triggering moment, it will be set to logic 0/1 at the triggering moment if the states of both the J and the K inputs are equal to logic 1 at the triggering moment.

4.14 Clocked J-K Flip Flop model: (a) Symbol for a SIMPLIS Clocked J-K flip flop, (b) Model for a SIMPLIS Clocked J-K flip flop.

Clocked Data Flip-Flop

.MODEL mname CLK_DFF TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}  TRIG_COND={0_TO_1 | 1_TO_0}

If TRIG_COND = 0_TO_1, the clocked data flip-flop is considered to be "triggered" when the logic state of the clock input changes from 0 to 1. Similarly, a logic 1 to logic 0 transition for the clock input is considered to "trigger" this type of flip-flop if TRIG_COND = 1_TO_0. The logic state of each output will not change except at the triggering moment. At the triggering moment, the logic state of the normal output Q will follow the logic state of the data input terminal.

4.15 Clocked Data Flip Flop model: (a) Symbol for a SIMPLIS Clocked Data flip flop, (b) Model for a SIMPLIS Clocked Data flip flop.

Clocked Toggle Flip-Flop

.MODEL mname CLK_TFF TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}  TRIG_COND={0_TO_1 | 1_TO_0}

If TRIG_COND = 0_TO_1, the clocked toggle flip-flop is considered to be "triggered" when the logic state of the clock input changes from 0 to 1. Similarly, a logic 1 to logic 0 transition for the clock input is considered to "trigger" this type of flip-flop if TRIG_COND = 1_TO_0. The logic state of each output will not change except at the triggering moment. At the triggering moment, the logic state of each output remains the same as the logic state before the triggering moment if the state of the toggle input is logic 0. On the other hand, the logic state of each output is complemented if the state of the toggle input is logic 1 at the triggering moment.

4.16 Clocked Toggle Flip Flop model: (a) Symbol for a SIMPLIS Clocked Toggle flip flop, (b) Model for a SIMPLIS Clocked Toggle flip flop.

Latch

.MODEL mname LATCH TH=threshold  HYSTWD=hystwd
+ VOL=vol  VOH=voh  RIN=rin  ROUT=rout
+ LOGIC={POS | NEG}  ENABLE_LEVEL={0 | 1}

If ENABLE_LEVEL = 1, the latch is considered to be "enabled" when the state of the enable input is logic 1. Similarly, if the state of the enable input is logic 0, a latch is considered to be "enabled" if ENABLE_LEVEL = 0. The logic state of the output will not change except when the latch is enabled. When the latch is enabled, the output logic state of the latch follows the logic state of the data input terminal.

4.17 Latch model: (a) Symbol for a SIMPLIS Latch, (b) Model for a SIMPLIS Latch.