Note
In this topic:
Mxxxx drain gate source bulk modelname [L=length] [W=width] + [AD=drain_area] [AS=source_area] + [PD=drain_perimeter] [PS=source_perimeter] + [NRD=drain_squares] [NRS=source_squares] + [NRB=bulk_squares] + [OFF] [IC=vds,vgs,vbs] [TEMP=local_temp] [M=area]
drain | Drain node |
gate | Gate node |
source | Source node |
bulk | Bulk (substrate) node |
modelname | Name of model. Must begin with a letter but can contain any character except whitespace and period '.' |
length | Channel length (metres). |
width | Channel width (metres). |
drain_area | Drain area (m2). |
source_area | Source area (m2). |
drain_perimeter | Drain perimeter (metres). |
source_perimeter | Source perimeter (metres). |
drain_squares | Equivalent number of squares for drain resistance |
source_squares | Equivalent number of squares for source resistance |
gate_squares | Equivalent number of squares for gate resistance. Level=3 only |
bulk_squares | Equivalent number of squares for gate resistance. Level=3 only |
OFF | Instructs simulator to calculate operating point analysis with device initially off. This is used in latching circuits such as thyristors and bistables to induce a particular state. See .OP for more details. |
vds, vgs, vbs | Initial condition voltages for drain-source gate-source and bulk(=substrate)-source respectively. These only have an effect if the UIC parameter is specified on the .TRAN statement. |
local_temp | Local temperature. Overrides specification in .OPTIONS or .TEMP statements. |
dtemp | Differential temperature. Similar to local_temp but is specified relative to circuit temperature. If both TEMP and DTEMP are specified, TEMP takes precedence. Currently implemented only for LEVEL 1,2 and 3. |
Notes | SIMetrix supports four types of MOSFET model specified in the model definition. These are referred to as levels 1, 2, 3 and 7. Levels 1,2, and 3 are the same as the SPICE2 and SPICE3 equivalents. Level 17 is proprietary to SIMetrix. For further information see Level 17 MOSFET parameters below. |
.model modelname NMOS ( level=level_number parameters )
.model modelname PMOS ( level=level_number parameters )
Name | Description | Units | Default | Levels | ||||||
VTO or VT0 | Threshold voltage | V | 0.0 | all | ||||||
KP | Transconductance parameter | A/V2 | 2.0e-5 | all | ||||||
GAMMA | Bulk threshold parameter | √V | 0.0 | all | ||||||
PHI | Surface potential | V | 0.6 | all | ||||||
LAMBDA | Channel length modulation | 1/V | 0.0 | all | ||||||
RG | Gate ohmic resistance | ???MATH???\Omega???MATH??? | 0.0 | 1,3 | ||||||
RD | Drain ohmic resistance | ???MATH???\Omega???MATH??? | 0.0 | all | ||||||
RS | Source ohmic resistance | ???MATH???\Omega???MATH??? | 0.0 | all | ||||||
RB | Bulk ohmic resistance | ???MATH???\Omega???MATH??? | 0.0 | 3 | ||||||
RDS | Drain-source shunt resistance | ???MATH???\Omega???MATH??? | ???MATH???\infty???MATH??? | 3 | ||||||
CBD | B-D junction capacitance | F | 0.0 | all | ||||||
CBS | B-S junction capacitance | F | 0.0 | all | ||||||
IS | Bulk junction sat. current | A | 1.0e-14 | all | ||||||
PB | Bulk junction potential | V | 0.8 | all | ||||||
CGSO | Gate-source overlap capacitance | F/m | 0.0 | all | ||||||
CGDO | Gate-drain overlap capacitance | F/m | 0.0 | all | ||||||
CGBO | Gate-bulk overlap capacitance | F/m | 0.0 | all | ||||||
RSH | Drain and source diffusion resistance | ???MATH???\Omega???MATH???/sq. | 0.0 | all | ||||||
CJ | Zero bias bulk junction bottom capacitance/sq-metre of junction area | F/m2 | See note | all | ||||||
MJ | Bulk junction bottom grading coefficient | 0.5 | all | |||||||
CJSW | Zero bias bulk junction sidewall capacitance | F/m | 0.0 | all | ||||||
MJSW | Bulk junction sidewall grading coefficient | 0.5 | 1 | |||||||
MJSW | as above | 0.33 | 2,3 | |||||||
JS | Bulk junction saturation current/sq-metre of junction area | A/m2 | 0.0 | all | ||||||
JSSW | Bulk p-n saturation sidewall current/length | A/m | 0.0 | 3 | ||||||
TT | Bulk p-n transit time | secs | 0.0 | 3 | ||||||
TOX | Oxide thickness | metre | 1e-7 | all | ||||||
NSUB | Substrate doping | 1/cm2 | 0.0 | all | ||||||
NSS | Surface state density | 1/cm2 | 0.0 | all | ||||||
NFS | Fast surface state density | 1/cm2 | 0.0 | 2,3 | ||||||
TPG |
Type of gate material:
|
all | ||||||||
XJ | Metallurgical junction depth | metre | 0.0 | 2,3 | ||||||
LD | Lateral diffusion | metre | 0.0 | all | ||||||
UO | Surface mobility | cm2/Vs | 600 | all | ||||||
UCRIT | Critical field for mobility | V/cm | 0.0 | 2 | ||||||
UEXP | Critical field exponent in mobility degradation | 0.0 | 2 | |||||||
UTRA | Transverse field coefficient (mobility) | 0.0 | 1,3 | |||||||
VMAX | Maximum drift velocity of carriers | m/s | 0.0 | 2,3 | ||||||
NEFF | Total channel charge (fixed and mobile) coefficient | 1.0 | 2 | |||||||
FC | Forward bias depletion capacitance coefficient | 0.5 | all | |||||||
TNOM, T_MEASURED | Reference temperature; the temperature at which the model parameters were measured | ???MATH???°???MATH???C | 27 | all | ||||||
T_ABS | If specified, defines the absolute model temperature overriding the global temperature defined using .TEMP | ???MATH???°???MATH???C | .TEMP | all | ||||||
T_REL_GLOBAL | Offsets global temperature defined using .TEMP. Overridden by T_ABS | ???MATH???°???MATH???C | 0.0 | all | ||||||
KF | Flicker noise coefficient | 0.0 | all | |||||||
AF | Flicker noise exponent | 1.0 | all | |||||||
DELTA | Width effect on threshold voltage | 0.0 | 2,3 | |||||||
THETA | Mobility modulation | 1/V | 0.0 | 3 | ||||||
ETA | Static feedback | 0.0 | 3 | |||||||
KAPPA | Saturation field factor | 0.2 | 3 | |||||||
W | Width | metre | DEFW | all | ||||||
L | Length | metre | DEFL | all | ||||||
NLEV | Noise model | 2 | all |
Two gate charge models are available for MOS Levels 1, 2 and 3 selectable by the .OPTIONS setting SPICEMOSCHARGEMODEL:
.OPTIONS SPICEMOSCHARGEMODEL=0|1
0 | Meyer capacitance model. This is the original model used in SPICE2 and SPICE3 and derivatives. The gate charge is defined by its capacitance and does not conserve charge |
1 | Yang-Chatterjee charge model. This is the model used by PSpice. It is charge based and as such does correctly conserve charge |
MOS level 1-3 models are predominantly used as part of many manufacturer-designed power MOS and IGBT subcircuit models. In most cases the choice of gate charge model is unimportant. However, for a few models, the results vary significantly with the choice of model used. Most models are designed for PSpice and so the safest choice is the Yang-Chatterjee charge model (.OPTIONS SPICEMOSCHARGEMODEL=1). However, SIMetrix version 8.0 and earlier do not support this model so for compatibility with earlier versions the Meyer capacitance model is the default.
The setting .OPTIONS SPICECOMPATIBILITY=2 automatically enables the Yang-Chatterjee charge model as the default.
The three levels 1 to 3 are as follows:
LEVEL 1 | Shichman-Hodges model. The simplest and is similar to the JFET model |
LEVEL 2 | A complex model which models the device according to an understanding of the device physics |
LEVEL 3 | Simpler than level 2. Uses a semi-empirical approach i.e. the device equations are partly based on observed effects rather than the theory governing its operation |
The above models differ from all other SIMetrix (and SPICE) models in that they contain many geometry relative parameters. The geometry of the device (length, width etc.) is entered on a per component basis and various electrical characteristics are calculated from parameters which are scaled according to those dimensions. This is approach is very much geared towards integrated circuit simulation and is inconvenient for discrete devices. If you are modelling a particular device by hand we recommend you use the level 17 model which is designed for discrete vertical devices.
Name | Description | Units | Default |
VTO or VT0 | Threshold voltage | V | 0.0 |
KP | Transconductance parameter | A/V2 | 2.0e-5 |
GAMMA | Bulk threshold parameter | ???MATH???\sqrt{\text{V}}???MATH??? | 0.0 |
PHI | Surface potential | V | 0.6 |
LAMBDA | Channel length modulation | 1/V | 0.0 |
RD | Drain ohmic resistance | ???MATH???\Omega???MATH??? | 0.0 |
RS | Source ohmic resistance | ???MATH???\Omega???MATH??? | 0.0 |
CBD | B-D junction capacitance | F | 0.0 |
CBS | B-S junction capacitance | F | 0.0 |
IS | Bulk junction sat. current | A | 1.0e-14 |
PB | Bulk junction potential | V | 0.8 |
CGSO | Gate-source overlap capacitance | F | 0.0 |
CGBO | Gate-bulk overlap capacitance | F | 0.0 |
CJ | Zero bias bulk junction bottom capacitance | F | 0.0 |
MJ | Bulk junction bottom grading coefficient | 0.5 | |
CJSW | Zero bias bulk junction sidewall capacitance | F | 0.0 |
MJSW | Bulk junction sidewall grading coefficient | 0.5 | |
FC | Forward bias depletion capacitance coefficient | 0.5 | |
TNOM | Parameter measurement temperature | ???MATH???°???MATH???C | 27 |
KF | Flicker noise coefficient | 0.0 | |
AF | Flicker noise exponent | 1.0 | |
CGDMAX | Maximum value of gate-drain capacitance | F | 0.0 |
CGDMIN | Minimum value of gate-drain capacitance | F | 0.0 |
XG1CGD | cgd max-min crossover gradient | 1.0 | |
XG2CGD | cgd max-min crossover gradient | 1.0 | |
VTCGD | cgd max-min crossover threshold voltage | V | 0.0 |
TC1RD | First order temperature coefficient of RD | 1/???MATH???°???MATH???C | 0.0 |
TC2RD | Second order temperature coefficient of RD | 1/???MATH???°???MATH???C2 | 0.0 |
In SIMetrix version 5.2 and earlier, this model used a level parameter value of 7 instead of the current 17. The number was changed so that a PSpice compatible BSIM3 model (level=7) could be offered. In order to retain backward compatibility, any level 7 model containing the parameters cgdmax, cgdmin, xg1cgd, xg2cgd or vtcgd will automatically be switched to level=17.
The level 17 MOSFET was developed to model discrete vertical MOS transistors rather than the integrated lateral devices that levels 1 to 3 are aimed at. Level 17 is based on level 1 but has the following important additions and changes:
Gate-drain capacitance equation:
\[ \begin{split} C_{gd} = \left(0.5 - \frac{1}{\pi}\tan^{-1}\left(\left(\text{VTCGD} - v\right) - \text{XG1CGD}\right)\right)\text{CGDMIN} \\ + \left(0.5 - \frac{1}{\pi}\tan^{-1}\left(\left(\text{VTCGD} - v\right)\text{XG2CGD}\right)\right)\text{CGDMAX} \end{split} \]
where ???MATH???v???MATH??? is the gate-drain voltage. This is an empirical formula devised to fit measured characteristics. Despite this it has been found to follow actual measured capacitance to remarkable accuracy.
To model gate-drain capacitance quickly and to acceptable accuracy set the five ???MATH???\text{C}_{\text{gd}}???MATH??? parameters as follows:
◄ Lossy Transmission Line | BSIM3 MOSFETs ▶ |