Arbitrary Logic Block

In this topic:

Netlist entry

Axxxx [ in_0 in_1 .. in_n ] [ out_0 out_1 .. out_n ]
+ model_name : parameters

Connection details

Name Description Flow Type
in Input in d, vector
out Output out d, vector

Instance Parameters

Name Description Type
trace_file Trace file string
user User device params real vector

Model format

.MODEL model_name d_logic_block parameters

Model parameters

Name Description Type Default Limits Vector bounds
file Definition file name string none none n/a
def Definition string none none n/a
out_delay Default output delay real 1n 1p ???MATH???- \infty???MATH??? n/a
reg_delay Default internal register delay real 1n ???MATH???0 - \infty???MATH??? n/a
setup_time Default level triggered setup time real 0 ???MATH???0 - \infty???MATH??? n/a
hold_time Default edge triggered hold time real 0 ???MATH???0 - \infty???MATH??? n/a
min_clock Default minimum clock width real 0 ???MATH???0 - \infty???MATH??? n/a
trace_file Trace log file string none n/a
user User defined parameters real vector none none none
user_scale Scale of user values real 1 ???MATH???0 - \infty???MATH??? n/a
input_load Input load value (F) real 1p none n/a
family Logic family string UNIV none n/a
in_family Input logic family string UNIV none n/a
out_family Output logic family string UNIV none n/a
out_res Digital output resistance real 100 ???MATH???0 - \infty???MATH??? n/a
out_res_pos Digital output res. pos. slope real out_res ???MATH???0 - \infty???MATH??? n/a
out_res_neg Digital output res. neg. slope out_res ???MATH???0 - \infty???MATH??? n/a
sink_current Input sink current real 0 none n/a
source_current Input source current real 0 none n/a

Device Operation

See Arbitrary Logic Block - User Defined Models.

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