The digital simulator only knows about the 12 logic states described in Logic States. It doesn't know anything about threshold voltages or output impedances and consequently cannot directly handle the effects of interconnecting devices from different logic families. It does however feature a mechanism of determining the level of compatibility between families and will raise an error if incompatible devices are interconnected. For example, ECL and high speed CMOS operate at completely different thresholds and cannot be connected except via a special interface gate. SIMetrix knows this so that if you attempt to connect such devices, an error message will be displayed and the simulation will not run. Conversely, it is perfectly OK to drive an LSTTL input from an HC output and SIMetrix will operate normally if you do so. If you drive an HC input from an LSTTL output SIMetrix will issue a warning as, although this may work in practice, it cannot be guaranteed to do so under all circumstances.
Another problem arises when connecting inputs from different logic families together. SIMetrix deals with this by treating groups of inputs as if they were all from the same logic family provided they are compatible. This selected logic family is then used to resolve any output-input conflict as described above. It is also used to select an analog-digital interface bridge as described in Analog to Digital Interfaces.
Groups of outputs from different families are dealt with in the same way as inputs described above.
SIMetrix knows how to resolve these situations by referring to a set of three tables called the 'Logic Compatibility Tables'. A standard set of tables is built in to the simulator but they can also be redefined. See Logic Compatibility Tables.
In this topic:
There are three model parameters used to specify the logic family to which a device belongs. These are:
| Parameter name | Description |
| IN_FAMILY | Family for inputs |
| OUT_FAMILY | Family for outputs |
| FAMILY | Family for both inputs and outputs if IN_FAMILY/OUT_FAMILY not specified |
The underscore character is used to define a sub-family that has the same characteristics as the main family as far as logic compatibility is concerned but which will call a different interface bridge when connected to an analog node. This is used to define schmitt trigger devices such as the 74HC14. In an all-digital circuit this behaves exactly like a normal inverter with a slightly longer delay. When the input is connected to an analog system an interface bridge with the appropriate hysteresis is called up instead of the normal interface.
As explained in the above section, there are three of these. Each table has a row and column entry for each of the logic families supported. These are:
For an example of a compatibility table, see the file COMPAT.TXT which you will find in the SCRIPT directory. This file is actually identical to the built-in definitions except for the UNIV family which cannot be redefined.
The file format consists of the following sections:
The names of all the logic families listed in one line. The names must not use the underscore ('_') character.
A table with the number of rows and columns equal to the number of logic families listed in the header. The columns represent outputs and the rows inputs. The entry in the table specifies the compatibility between the output and the input when connected to each other. The entry may be one of three values:
| Value | Meaning |
| OK | Fully compatible |
| WARN | Not compatible but would usually function. Warn user but allow simulation to continue. |
| ERR | Not compatible and would never function. Abort simulation. |
A table with the number of rows and columns equal to the number of logic families listed in the header. Both column and rows represent inputs. The table defines how inputs from different families are treated when they are connected. The entry may be one of four values:
| Value | Meaning |
| ROW | Row take precedence |
| COL | Column takes precedence |
| OK | Doesn't matter. (Currently identical to ROW) |
| ERR | Incompatible, inputs cannot be connected. |
A table with the number of rows and columns equal to the number of logic families listed in the header. Both column and rows represent outputs. The table defines how outputs from different families are treated when they are connected. The entry may be one of four values:
| Value | Meaning |
| ROW | Row take precedence |
| COL | Column takes precedence |
| OK | Doesn't matter. (Currently identical to ROW) |
| ERR | Incompatible, outputs cannot be connected. |
The following logic families are supported by the internal Logic Compatibility Tables.
| Family name | Description |
| TTL | TTL - 74 series |
| HC | High speed CMOS - 74HC series |
| HCT | TTL compatible High speed CMOS - 74HCT series |
| FAST | FAST TTL - 74F series |
| LS | Low power schottky TTL - 74LS series |
| ALS | Advanced low power schottky TTL - 74ALS series |
| 4000-5 | 4000 series CMOS - 5V operation |
| 4000-10 | 4000 series CMOS - 10V operation |
| 4000-15 | 4000 series CMOS - 15V operation |
| ECL10K | ECL 10K series |
| ECL10KE | ECL Eclipse series |
| AC | Advanced CMOS - 74AC series |
| ACT | TTL compatible Advanced CMOS - 74ACT series |
| FORCE5 | Used for 5V VCC rails. |
| UNIV | Universal family - see below |
The internal tables support the concept of a 'Universal logic family'. This is called UNIV and can connect to any logic family without error. This is the default if no FAMILY parameter is supplied.
The internal tables are documented in the on-line help system. Refer to topic "Internal Tables" which is listed as a keyword in the index tab.
| ◄ Analog to Digital Interfaces | Load Delay ▶ |