And Gate

In this topic:

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details

Name Description Flow Type Vector bounds
in Input in d, vector ???MATH???2 - \infty???MATH???
out Output out d n/a

Model format

.MODEL model_name d_and parameters

Model parameters

Name Description Type Default Limits
rise_delay Rise delay real 1nS 1e-12 - ???MATH???\infty???MATH???
fall_delay Fall delay real 1nS 1e-12 - ???MATH???\infty???MATH???
input_load Input load value (F) real 1pF none
family Logic family string UNIV none
in_family Input logic family string UNIV none
out_family Output logic family string UNIV none
out_res Digital output resistance real 100 ???MATH???0 - \infty???MATH???
out_res_pos Digital output res. pos. slope real out_res ???MATH???0 - \infty???MATH???
out_res_neg Digital output res. neg. slope out_res ???MATH???0 - \infty???MATH???
open_c Open collector output boolean FALSE none
min_sink Minimum sink current real -0.001 none
max_source Maximum source current real 0.001 none
sink_current Input sink current real 0 none
source_current Input source current real 0 none

Device operation

  • If the model parameter OPEN_C is false, The output will be at logic '0' if either input is at logic '0'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '1'.
  • If the model parameter OPEN_C is true the device will be open collector. In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '0' the output strength will be STRONG. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state.
◄ Digital Device Overview   D-type Latch ▶