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The SIMetrix schematic editor provides a feature that will create and place a schematic symbol from a Verilog file. This feature reads the Verilog file and determines the inputs and outputs along with the names of the ports. It also reads any parameters defined. From this information it creates a symbol with inputs on the left and outputs on the right. It also creates an edit facility to edit any parameters defined in the Verilog module.
To create a schematic symbol from a Verilog design, proceed as follows:
*** ERROR *** Cannot parse verilog design file 'filename'. For details see log file 'filename.log'
Cannot parse Verilog-HDL file. No symbol created.
The log file should list details of the error. This file is generated by the GPL Cver Verilog simulator and will contain additional information that can obscure the desired error message. Verilog errors must be rectified before SIMetrix can create a symbol.
The symbol creation feature described above builds the necessary functionality in the symbol to allow GUI editing of the device's parameters. To use this, just edit the schematic instance in the usual way by double clicking or selecting followed by F7.
You will see a dialog box showing a number of parameters. The first parameters starting with 'Voltage input logic zero threshold' and ending with 'Threshold time tolerance' along with the check boxes 'Disable output of non-analog vectors' and 'Disable Module Cache' are built-in parameters that are defined for all Verilog devices. Any parameters defined within the Verilog definition will be shown in addition to these and listed after 'Threshold time tolerance'.
| ◄ Basic Operation | Module Cache ▶ |