| Name | Description | Type | Default | Limits | 
              
                | delay | Delay | real | 1nS | ???MATH???1\text{e}^{-12} - \infty???MATH??? | 
              
                | input_load | Input load value (F) | real | 1pF | none | 
              
                | enable_load | Enable load value (F) | real | 1pF | none | 
              
                | family | Logic family | string | UNIV | none | 
              
                | in_family | Input logic family | string | UNIV | none | 
              
                | out_family | Output logic family | string | UNIV | none | 
              
                | out_res | Digital output resistance | real | 100 | ???MATH???0 - \infty???MATH??? | 
              
                | out_res_pos | Digital output res. pos. slope | real | out_res | ???MATH???0 - \infty???MATH??? | 
              
                | out_res_neg | Digital output res. neg. slope | real | out_res | ???MATH???0 - \infty???MATH??? | 
              
                | min_sink | Minimum sink current | real | -0.001 | none | 
              
                | max_source | Maximum source current | real | 0.001 | none | 
              
                | sink_current | Input sink current | real | 0 | none | 
              
                | source_current | Input source current | real | 0 | none |