SIMPLIS includes a library of discrete time filters used for modeling digital control loops. These filters process analog control signals, producing outputs with the desired z-domain transfer functions. The discrete time filters are compatible with the POP and AC analyses, allowing direct simulation of digital control-loop behavior.
Devices in the library include:
Each of the discrete time filters is driven by an input clock signal.
A schematic of the connection between a Sampling Clock Generator for Discrete Filters and a 1st Order Discrete Time Filter is shown below.
This example can be downloaded here: simplis_034_1stordfilter_example
This timing behavior is described by the waveforms below:
A discrete filter with more than two poles can be synthesized through a cascade of one-pole and/or two-pole discrete filters. In that case, the timing signal for each driven stage is derived from the CLK_OUT signal of the immediately preceding stage. A schematic using cascaded connections of a 1st Order Discrete Time Filter and a 2nd Order Discrete Time Filter is shown below.
This example can be downloaded here: simplis_001_cascaded_filters_example