The Down Counter models a generic down counter with between 2 and 32 output bits.
For a counter which counts up, see Up Counter. For a counter that counts up or down, see Up/Down Counter.
Model Name: | Down Counter | |||
Simulator: | This device is compatible with the SIMPLIS simulator. | |||
Parts Selector Menu Location: | ||||
Symbol Library: | None - the symbol is automatically generated when placed or edited. | |||
Model Library: | None - the model is automatically generated when the simulation is run. | |||
Subcircuit Names: |
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Symbol: |
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Multiple Selections: | Only one device at a time can be edited. |
To configure the Down Counter, follow these steps:
Label | Parameter Description | ||||||
Clock to Output Delay | Delay from the triggering clock event until the Counter outputs change | ||||||
Number of Bits | Number of output bits for the Counter | ||||||
Trigger Condition | Determines the
triggering condition of the Counter clock pin:
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Ground Ref | Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic. | ||||||
Minimum Clk Width | Minimum valid clock width. Clock widths less than this parameter will not trigger the Counter. | ||||||
Enable Delay | Delay from when the enable pin goes active until the output is enabled | ||||||
Setup Time | Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | ||||||
Hold Time | Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | ||||||
Initial Condition | Initial condition of the Counter output at time=0 | ||||||
Set Delay | Delay from when the SET pin goes active until the counter output is reset | ||||||
Set To | Determines the value of the counter output when the SET pin goes active. To set to the maximum count value, assign a value of -1. | ||||||
Set Level | Determines the Set
level of counter SET input pin:
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Set Type | Determines whether or
not reset events are synchronized with a clock event
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To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps:
Label | Parameter Description | |||||||
Input Resistance | Input resistance of each Counter input pin | |||||||
Hysteresis, Threshold | Hysteresis and
Threshold of the inputs. The hysteretic-window width, HYSTWD
is centered around Threshold (TH) voltage. To
determine the actual threshold ( TL , THI ),
substitute Threshold (TH) and Hysteresis
(HYSTWD) in each of the following formulas:
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Output Resistance | Output resistance of each Counter output pin | |||||||
Output High Voltage | Output high voltage for each Counter output pin | |||||||
Output Low Voltage | Output high voltage for each Counter output pin |
The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked counter.
Inputs | Outputs | Action | ||
EN | SET | CLK | D0..Dn | |
1 | 0 | Count - 1 | Count down | |
0 | 0 | Last count | Retain last count | |
0 | 1 | 0 or 1 | Set To parameter value | Set the counter to the Set To parameter value |
The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_029_downcounter_example.sxsch.
Because the Down Counter model is generated by a template script when the simulation is executed, a hand-coded model cannot be inserted into a netlist. The template script for this device is simplis_make_counter_model.sxscr, which licensed users can download as part of a zip archive of all built-in scripts.
To download the zip archive, follow these steps:
The following parameter table defines the parameters used in this model.
Parameter Name | Label | Data Type | Range | Units | Parameter Description | |||||||
CLK_TO_OUT_DELAY | Clock to Output Delay | Number | 1f to 1024 | s | Delay from the triggering clock event until the Counter outputs change | |||||||
ENABLE_DELAY | Enable Delay | Number | any | s | Delay from when the enable pin goes active until the output is enabled | |||||||
GNDREF | Ground Ref | String |
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none | Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic. | |||||||
HOLD_TIME | Hold Time | Number | 1f to 1024 | s | Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | |||||||
HYSTWD, TH |
Hysteresis, Threshold |
Number | min: 1f | V | Hysteresis and Threshold of
the inputs. The hysteretic-window width, HYSTWD is centered around
Threshold (TH) voltage. To determine the actual threshold (
TL , THI ), substitute Threshold (TH) and
Hysteresis (HYSTWD) in each of the following formulas:
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IC | Initial Condition | Number |
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none | Initial condition of the Counter output at time=0 | |||||||
MIN_CLK | Minimum Clk Width | Number | 1f to 1024 | s | Minimum valid clock width. Clock widths less than this parameter will not trigger the Counter. | |||||||
NUMBITS | Number of Bits | Integer | none | Number of output bits for the Counter | ||||||||
RIN | Input Resistance | Number | min: 100 | Ω | Input resistance of each Counter input pin | |||||||
ROUT | Output Resistance | Number | min: 1m | Ω | Output resistance of each Counter output pin | |||||||
SETUP_TIME | Setup Time | Number | 1f to 1024 | s | Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized. | |||||||
SET_DELAY | Set Delay | Number | any | s | Delay from when the SET pin goes active until the counter output is reset | |||||||
SET_LEVEL | Set Level | Integer | none | Determines the Set level of
counter SET input pin:
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SET_TO | Set To | Number | none | Determines the value of the counter output when the SET pin goes active. To set to the maximum count value, assign a value of -1. | ||||||||
SET_TYPE | Set Type | String |
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none | Determines whether or not
reset events are synchronized with a clock event
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TRIG_COND | Trigger Condition | String |
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none | Determines the triggering
condition of the Counter clock pin:
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VOH | Output High Voltage | Number | any | V | Output high voltage for each Counter output pin | |||||||
VOL | Output Low Voltage | Number | any | V | Output high voltage for each Counter output pin |