Up/Down Counter

The Up/Down Counter models a generic up or down counter with between 2 and 32 output bits. The direction of the counter is based on the CNT_UP pin.

  • On each clock edge, the D0 ... Dn outputs can increase or decrease one count or hold the last count, depending on the EN pin.
  • The clock-edge trigger can be set with the Trigger Condition parameter to be either rising edge (0_TO_1) or falling edge (1_TO_0).
  • The counter may also be set or reset to a value with the SET or RST pin. When the SET or RST pin goes active, the counter changes to the value specified by the Set To or Reset To parameters, respectively.
  • The Set/Reset Type parameter controls whether the set event is asynchronous or synchronous to the CLK edge.

For a counter which counts up, see the Up Counter. For a counter that counts down, see Down Counter.

In this topic:

Model Name: Up/Down Counter
Simulator: This device is compatible with the SIMPLIS simulator.
Parts Selector Menu Location: Digital Functions > Counters
Symbol Library: None - the symbol is automatically generated when placed or edited.
Model Library: None - the model is automatically generated when the simulation is run.
Subcircuit Names:
  • SIMPLIS_DIGI1_D_UPDOWN_COUNTER_N : Without Ground Reference
  • SIMPLIS_DIGI1_D_UPDOWN_COUNTER_Y : With Ground Reference
Symbol:
3-bit, rising edge triggered without ground reference.
Multiple Selections: Only one device at a time can be edited.

Editing the Up/Down Counter

To configure the Up/Down Counter, follow these steps:

  1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description
Clock to Output Delay Delay from the triggering clock event until the Counter outputs change
Number of Bits Number of output bits for the Counter
Trigger Condition Determines the triggering condition of the Counter clock pin:
  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered
Ground Ref Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic.
Minimum Clk Width Minimum valid clock width. Clock widths less than this parameter will not trigger the Counter.
Enable Delay Delay from when the enable pin goes active until the output is enabled
Setup Time Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.
Hold Time Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.
Initial Condition Initial condition of the Counter output at time=0
Set/Reset Delay Delay from when the SET or RST pin goes active until the Q output is actually set or reset.
Set To Determines the value of the counter output when the SET pin goes active. To set to the maximum count value, assign a value of -1.
Reset To Determines the value of the counter output when the RST pin goes active. To reset to 0, assign a assign value of -1 or 0.
Set/Reset Level Determines the Set/Reset level of a device:
  • 1 means active high
  • 0 means active low
Set/Reset Type Determines whether or not output events are synchronized with a clock event:
Set/Reset Type Description
SYNC Set/reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNC Set/reset events are asynchronous to the clock edge.
.

To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps:

  1. From the Edit Up/Down Counter dialog box, click on the Interface tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description
Input Resistance Input resistance of each Counter input pin
Hysteresis, Threshold Hysteresis and Threshold of the inputs. The hysteretic-window width, HYSTWD is centered around Threshold (TH) voltage. To determine the actual threshold ( TL , THI ), substitute Threshold (TH) and Hysteresis (HYSTWD) in each of the following formulas:
Input Logic Level Actual Threshold
1 Threshold + 0.5 * Hysteresis
0 Threshold - 0.5 * Hysteresis
Output Resistance Output resistance of each Counter output pin
Output High Voltage Output high voltage for each Counter output pin
Output Low Voltage Output high voltage for each Counter output pin

Truth Table

The following truth table assumes a Trigger Condition=0_TO_1 which represents a rising edge clocked counter.

Inputs Outputs Action
EN SET RST CNT_UP CLK D0..Dn
1 0 0 0
Count - 1 Count down
1 0 0 1
Count + 1 Count up
0 0 0 0 0 or 1 Last count Retain last count
0 or 1 1 0 0 or 1 0 or 1 Set To parameter value Set the counter to the Set To parameter value
0 or 1 0 1 0 or 1 0 or 1 Reset To parameter value Set the counter to the Reset To parameter value

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_030_updowncounter_example.sxsch.

Waveforms

Subcircuit Parameters

Because the Up/Down Counter model is generated by a template script when the simulation is executed, a hand-coded model cannot be inserted into a netlist. The template script for this device is simplis_make_counter_model.sxscr, which licensed users can download as part of a zip archive of all built-in scripts.

To download the zip archive, follow these steps:

Important: You will be prompted to log in with the user name and password you received with your license file. If you don't have the user name and password, you can email support@simplistechnologies.com with your license information to receive the login credentials. Include a screenshot of the dialog which opens when you run the Help > License Diagnostics... menu.
  1. Click http://www.simetrix.co.uk/simetrix80/scripts.zip to download the script archive.
  2. Enter the user name and password you received with your license file.

The following parameter table defines the parameters used in this model.

Parameter Name Label Data Type Range Units Parameter Description
CLK_TO_OUT_DELAY Clock to Output Delay Number 1f to 1024 s Delay from the triggering clock event until the Counter outputs change
ENABLE_DELAY Enable Delay Number any s Delay from when the enable pin goes active until the output is enabled
GNDREF Ground Ref String
  • 'Y'
  • 'N'
 none Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic.
HOLD_TIME Hold Time Number 1f to 1024 s Minimum time after the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.
HYSTWD,
TH		 Hysteresis,
Threshold		 Number min: 1f V Hysteresis and Threshold of the inputs. The hysteretic-window width, HYSTWD is centered around Threshold (TH) voltage. To determine the actual threshold ( TL , THI ), substitute Threshold (TH) and Hysteresis (HYSTWD) in each of the following formulas:
Input Logic Level Actual Threshold
1 Threshold + 0.5 * Hysteresis
0 Threshold - 0.5 * Hysteresis
IC Initial Condition Number
  • 0
  • 1
 none Initial condition of the Counter output at time=0
MIN_CLK Minimum Clk Width Number 1f to 1024 s Minimum valid clock width. Clock widths less than this parameter will not trigger the Counter.
NUMBITS Number of Bits Integer   none Number of output bits for the Counter
RESET_TO Reset To Number   none Determines the value of the counter output when the RST pin goes active. To reset to 0, assign a assign value of -1 or 0.
RIN Input Resistance Number min: 100 Ω Input resistance of each Counter input pin
ROUT Output Resistance Number min: 1m Ω Output resistance of each Counter output pin
SETUP_TIME Setup Time Number 1f to 1024 s Minimum time before the triggering clock event that the input signals must remain steady so that a valid change in each input state is recognized.
SET_RESET_DELAY Set/Reset Delay Number 1f to 1024 s Delay from when the SET or RST pin goes active until the Q output is actually set or reset.
SET_RESET_LEVEL Set/Reset Level Number
  • 0
  • 1
 none Determines the Set/Reset level of a device:
  • 1 means active high
  • 0 means active low
SET_RESET_TYPE Set/Reset Type String
  • 'SYNC'
  • 'ASYNC'
 none Determines whether or not output events are synchronized with a clock event:
Set/Reset Type Description
SYNC Set/reset events are synchronized to the clock edge defined by the Trigger Condition parameter.
ASYNC Set/reset events are asynchronous to the clock edge.
.
SET_TO Set To Number   none Determines the value of the counter output when the SET pin goes active. To set to the maximum count value, assign a value of -1.
TRIG_COND Trigger Condition String
  • '0_TO_1'
  • '1_TO_0'
 none Determines the triggering condition of the Counter clock pin:
  • 0_TO_1 for rising edge triggered
  • 1_TO_0 for falling edge triggered
VOH Output High Voltage Number any V Output high voltage for each Counter output pin
VOL Output Low Voltage Number any V Output high voltage for each Counter output pin